X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTools.hs;h=e7c598d498d322222821bdaf091422ca778e5f96;hb=aa23b0116eaf65b01499cd1eba93a92f7c8c36e8;hp=3a6060d302bc7a5f850bfeaa13d6532c15ffbc25;hpb=8782caddd5cc4df0c68e4025266c9b558e32eb48;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/VHDLTools.hs b/VHDLTools.hs index 3a6060d..e7c598d 100644 --- a/VHDLTools.hs +++ b/VHDLTools.hs @@ -7,6 +7,7 @@ import qualified Data.List as List import qualified Data.Map as Map import qualified Control.Monad as Monad import qualified Control.Arrow as Arrow +import qualified Control.Monad.Trans.State as State import qualified Data.Monoid as Monoid import Data.Accessor import Debug.Trace @@ -20,6 +21,7 @@ import qualified Name import qualified OccName import qualified Var import qualified Id +import qualified IdInfo import qualified TyCon import qualified Type import qualified DataCon @@ -121,8 +123,8 @@ mkComponentInst label entity_id portassigns = AST.CSISm compins ----------------------------------------------------------------------------- -- Turn a variable reference into a AST expression -varToVHDLExpr :: Var.Var -> AST.Expr -varToVHDLExpr var = +varToVHDLExpr :: TypeState -> Var.Var -> AST.Expr +varToVHDLExpr ty_state var = case Id.isDataConWorkId_maybe var of Just dc -> dataconToVHDLExpr dc -- This is a dataconstructor. @@ -132,17 +134,18 @@ varToVHDLExpr var = -- should still be translated to integer literals. It is probebly not the -- best solution to translate them here. -- FIXME: Find a better solution for translating instances of tfp integers - Nothing -> + Nothing -> let ty = Var.varType var res = case Type.splitTyConApp_maybe ty of Just (tycon, args) -> case Name.getOccString (TyCon.tyConName tycon) of - "Dec" -> AST.PrimLit $ (show (eval_tfp_int ty)) + "Dec" -> AST.PrimLit $ (show (fst ( State.runState (tfp_to_int ty) ty_state ) ) ) otherwise -> AST.PrimName $ AST.NSimple $ varToVHDLId var in res + -- Turn a VHDLName into an AST expression vhdlNameToVHDLExpr = AST.PrimName @@ -150,7 +153,7 @@ vhdlNameToVHDLExpr = AST.PrimName idToVHDLExpr = vhdlNameToVHDLExpr . AST.NSimple -- Turn a Core expression into an AST expression -exprToVHDLExpr = varToVHDLExpr . exprToVar +exprToVHDLExpr ty_state = (varToVHDLExpr ty_state) . exprToVar -- Turn a alternative constructor into an AST expression. For -- dataconstructors, this is only the constructor itself, not any arguments it @@ -315,7 +318,10 @@ construct_vhdl_ty ty = do case name of "TFVec" -> mk_vector_ty ty "SizedWord" -> mk_unsigned_ty ty - "RangedWord" -> mk_natural_ty 0 (ranged_word_bound ty) + "SizedInt" -> mk_signed_ty ty + "RangedWord" -> do + bound <- tfp_to_int (ranged_word_bound_ty ty) + mk_natural_ty 0 bound -- Create a custom type from this tycon otherwise -> mk_tycon_ty tycon args Nothing -> return (Left $ "VHDLTools.construct_vhdl_ty: Cannot create type for non-tycon type: " ++ pprString ty ++ "\n") @@ -367,10 +373,11 @@ mk_vector_ty :: mk_vector_ty ty = do types_map <- getA vsTypes + env <- getA vsHscEnv let (nvec_l, nvec_el) = Type.splitAppTy ty let (nvec, leng) = Type.splitAppTy nvec_l let vec_ty = Type.mkAppTy nvec nvec_el - let len = tfvec_len ty + len <- tfp_to_int (tfvec_len_ty ty) let el_ty = tfvec_elem ty el_ty_tm_either <- vhdl_ty_either el_ty case el_ty_tm_either of @@ -407,12 +414,22 @@ mk_natural_ty min_bound max_bound = do return (Right (ty_id, Right ty_def)) mk_unsigned_ty :: - Type.Type -- ^ Haskell type of the signed integer + Type.Type -- ^ Haskell type of the unsigned integer -> TypeSession (Either String (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn)) mk_unsigned_ty ty = do - let size = sized_word_len ty + size <- tfp_to_int (sized_word_len_ty ty) let ty_id = mkVHDLExtId $ "unsigned_" ++ show (size - 1) let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))] + let ty_def = AST.SubtypeIn unsignedTM (Just range) + return (Right (ty_id, Right ty_def)) + +mk_signed_ty :: + Type.Type -- ^ Haskell type of the signed integer + -> TypeSession (Either String (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn)) +mk_signed_ty ty = do + size <- tfp_to_int (sized_int_len_ty ty) + let ty_id = mkVHDLExtId $ "signed_" ++ show (size - 1) + let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))] let ty_def = AST.SubtypeIn signedTM (Just range) return (Right (ty_id, Right ty_def)) @@ -456,14 +473,21 @@ mkHType ty = do case elem_htype_either of -- Could create element type Right elem_htype -> do - len <- vec_len ty + len <- tfp_to_int (tfvec_len_ty ty) return $ Right $ VecType len elem_htype -- Could not create element type Left err -> return $ Left $ "VHDLTools.mkHType: Can not construct vectortype for elementtype: " ++ pprString el_ty ++ "\n" ++ err - "SizedWord" -> return $ Right $ StdType $ OrdType ty - "RangedWord" -> return $ Right $ StdType $ OrdType ty + "SizedWord" -> do + len <- tfp_to_int (sized_word_len_ty ty) + return $ Right $ SizedWType len + "SizedInt" -> do + len <- tfp_to_int (sized_word_len_ty ty) + return $ Right $ SizedIType len + "RangedWord" -> do + bound <- tfp_to_int (ranged_word_bound_ty ty) + return $ Right $ RangedWType bound otherwise -> do mkTyConHType tycon args Nothing -> return $ Right $ StdType $ OrdType ty @@ -499,14 +523,15 @@ isReprType ty = do Left _ -> False Right _ -> True -vec_len :: Type.Type -> TypeSession Int -vec_len ty = do - veclens <- getA vsTfpInts - let len_ty = tfvec_len_ty ty - let existing_len = Map.lookup (OrdType len_ty) veclens +tfp_to_int :: Type.Type -> TypeSession Int +tfp_to_int ty = do + lens <- getA vsTfpInts + hscenv <- getA vsHscEnv + let norm_ty = normalise_tfp_int hscenv ty + let existing_len = Map.lookup (OrdType norm_ty) lens case existing_len of Just len -> return len Nothing -> do - let new_len = tfvec_len ty - modA vsTfpInts (Map.insert (OrdType len_ty) (new_len)) + let new_len = eval_tfp_int hscenv ty + modA vsTfpInts (Map.insert (OrdType norm_ty) (new_len)) return new_len \ No newline at end of file