X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTools.hs;h=a66f92dd4592d181152343909b72393a8d39948f;hb=1d2f36c370db9ef82667741cc9414f9896084af3;hp=1e6e5bc1d09e6a956bb5b53fc7039e2985afb406;hpb=758998d6ef18ab5124c65518781c358d76d229ab;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTools.hs b/VHDLTools.hs
index 1e6e5bc..a66f92d 100644
--- a/VHDLTools.hs
+++ b/VHDLTools.hs
@@ -527,10 +527,11 @@ isReprType ty = do
 tfp_to_int :: Type.Type -> TypeSession Int
 tfp_to_int ty = do
   lens <- getA vsTfpInts
+  hscenv <- getA vsHscEnv
   let existing_len = Map.lookup (OrdType ty) lens
   case existing_len of
     Just len -> return len
     Nothing -> do
-      let new_len = eval_tfp_int ty
+      let new_len = eval_tfp_int hscenv ty
       modA vsTfpInts (Map.insert (OrdType ty) (new_len))
       return new_len
\ No newline at end of file