X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTools.hs;h=8bc45f79a43490cb3f45c6e0ac3389d58337e085;hb=e091fb6b78ed5ea074e4c41879a712a806771ba4;hp=359597f3395485f1ad96b525da9e4b837cbc14ca;hpb=6fcd2ccf28d4b34eca94eb868ecac83cc5a2c144;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTools.hs b/VHDLTools.hs
index 359597f..8bc45f7 100644
--- a/VHDLTools.hs
+++ b/VHDLTools.hs
@@ -479,3 +479,11 @@ mkTyConHType tycon args =
   where
     tyvars = TyCon.tyConTyVars tycon
     subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
+
+-- Is the given type representable at runtime?
+isReprType :: Type.Type -> TypeSession Bool
+isReprType ty = do
+  ty_either <- vhdl_ty_either ty
+  return $ case ty_either of
+    Left _ -> False
+    Right _ -> True