X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=ee61c500a6916f676fd75e1c7566d6d8bb868eab;hb=157dae90bdd7c45613c6ad6185383a1137b2323f;hp=5516d00b3729fad13937939eaab9d9fe4f95156a;hpb=4c4b23981da0a67031547c8ff7e4b2a43698dd46;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/VHDL.hs b/VHDL.hs index 5516d00..ee61c50 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -3,9 +3,9 @@ -- module VHDL where -import Data.Traversable import qualified Data.Foldable as Foldable import qualified Maybe +import qualified Control.Monad as Monad import qualified Type import qualified Name @@ -15,33 +15,36 @@ import Outputable ( showSDoc, ppr ) import qualified ForSyDe.Backend.VHDL.AST as AST import VHDLTypes +import Flatten import FlattenTypes import TranslatorTypes +import Pretty -- | Create an entity for a given function createEntity :: HsFunction -- | The function signature -> FuncData -- | The function data collected so far - -> FuncData -- | The modified function data + -> VHDLState () createEntity hsfunc fdata = let func = flatFunc fdata in case func of -- Skip (builtin) functions without a FlatFunction - Nothing -> fdata + Nothing -> do return () -- Create an entity for all other functions Just flatfunc -> let - s = sigs flatfunc - a = args flatfunc - r = res flatfunc - args' = map (fmap (mkMap s)) a - res' = fmap (mkMap s) r + sigs = flat_sigs flatfunc + args = flat_args flatfunc + res = flat_res flatfunc + args' = map (fmap (mkMap sigs)) args + res' = fmap (mkMap sigs) res ent_decl' = createEntityAST hsfunc args' res' - entity' = Entity args' res' (Just ent_decl') + AST.EntityDec entity_id _ = ent_decl' + entity' = Entity entity_id args' res' (Just ent_decl') in - fdata { entity = Just entity' } + setEntity hsfunc entity' where mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark) mkMap sigmap id = @@ -55,7 +58,7 @@ createEntity hsfunc fdata = (sigName info) ty = sigTy info --- | Create the VHDL AST for an entity + -- | Create the VHDL AST for an entity createEntityAST :: HsFunction -- | The signature of the function we're working with -> [VHDLSignalMap] -- | The entity's arguments @@ -68,9 +71,16 @@ createEntityAST hsfunc args res = vhdl_id = mkEntityId hsfunc ports = concatMap (mapToPorts AST.In) args ++ mapToPorts AST.Out res + ++ clk_port mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] mapToPorts mode m = map (mkIfaceSigDec mode) (Foldable.toList m) + -- Add a clk port if we have state + clk_port = if hasState hsfunc + then + [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty] + else + [] -- | Create a port declaration mkIfaceSigDec :: @@ -85,21 +95,152 @@ mkEntityId hsfunc = -- TODO: This doesn't work for functions with multiple signatures! mkVHDLId $ hsFuncName hsfunc +-- | Create an architecture for a given function +createArchitecture :: + HsFunction -- | The function signature + -> FuncData -- | The function data collected so far + -> VHDLState () + +createArchitecture hsfunc fdata = + let func = flatFunc fdata in + case func of + -- Skip (builtin) functions without a FlatFunction + Nothing -> do return () + -- Create an architecture for all other functions + Just flatfunc -> do + let sigs = flat_sigs flatfunc + let args = flat_args flatfunc + let res = flat_res flatfunc + let apps = flat_apps flatfunc + let entity_id = Maybe.fromMaybe + (error $ "Building architecture without an entity? This should not happen!") + (getEntityId fdata) + -- Create signal declarations for all signals that are not in args and + -- res + let sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ] + -- Create component instantiations for all function applications + insts <- mapM (mkCompInsSm sigs) apps + let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc) + let insts' = map AST.CSISm insts + let procs' = map AST.CSPSm procs + let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (insts' ++ procs') + setArchitecture hsfunc arch + +mkStateProcSm :: (Int, SignalInfo, SignalInfo) -> AST.ProcSm +mkStateProcSm (num, old, new) = + AST.ProcSm label [clk] [statement] + where + label = mkVHDLId $ "state_" ++ (show num) + clk = mkVHDLId "clk" + rising_edge = AST.NSimple $ mkVHDLId "rising_edge" + wform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple $ getSignalId new) Nothing] + assign = AST.SigAssign (AST.NSimple $ getSignalId old) wform + rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)] + statement = AST.IfSm rising_edge_clk [assign] [] Nothing + +mkSigDec :: SignalInfo -> AST.SigDec +mkSigDec info = + AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing + where + ty = sigTy info + +-- | Creates a VHDL Id from a named SignalInfo. Errors out if the SignalInfo +-- is not named. +getSignalId :: SignalInfo -> AST.VHDLId +getSignalId info = + mkVHDLId $ Maybe.fromMaybe + (error $ "Unnamed signal? This should not happen!") + (sigName info) + +-- | Transforms a flat function application to a VHDL component instantiation. +mkCompInsSm :: + [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture + -> FApp UnnamedSignal -- | The application to look at. + -> VHDLState AST.CompInsSm -- | The corresponding VHDL component instantiation. + +mkCompInsSm sigs app = do + let hsfunc = appFunc app + fdata_maybe <- getFunc hsfunc + let fdata = Maybe.fromMaybe + (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' that is not in the session? This should not happen!") + fdata_maybe + let entity = Maybe.fromMaybe + (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' without entity declaration? This should not happen!") + (funcEntity fdata) + let entity_id = ent_id entity + label <- uniqueName (AST.fromVHDLId entity_id) + let portmaps = mkAssocElems sigs app entity + return $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps) + +mkAssocElems :: + [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture + -> FApp UnnamedSignal -- | The application to look at. + -> Entity -- | The entity to map against. + -> [AST.AssocElem] -- | The resulting port maps + +mkAssocElems sigmap app entity = + -- Create the actual AssocElems + zipWith mkAssocElem ports sigs + where + -- Turn the ports and signals from a map into a flat list. This works, + -- since the maps must have an identical form by definition. TODO: Check + -- the similar form? + arg_ports = concat (map Foldable.toList (ent_args entity)) + res_ports = Foldable.toList (ent_res entity) + arg_sigs = (concat (map Foldable.toList (appArgs app))) + res_sigs = Foldable.toList (appRes app) + -- Extract the id part from the (id, type) tuple + ports = (map fst (arg_ports ++ res_ports)) + -- Translate signal numbers into names + sigs = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs)) + +-- | Look up a signal in the signal name map +lookupSigName :: [(UnnamedSignal, SignalInfo)] -> UnnamedSignal -> String +lookupSigName sigs sig = name + where + info = Maybe.fromMaybe + (error $ "Unknown signal " ++ (show sig) ++ " used? This should not happen!") + (lookup sig sigs) + name = Maybe.fromMaybe + (error $ "Unnamed signal " ++ (show sig) ++ " used? This should not happen!") + (sigName info) + +-- | Create an VHDL port -> signal association +mkAssocElem :: AST.VHDLId -> String -> AST.AssocElem +mkAssocElem port signal = Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) + +-- | Extracts the generated entity id from the given funcdata +getEntityId :: FuncData -> Maybe AST.VHDLId +getEntityId fdata = + case funcEntity fdata of + Nothing -> Nothing + Just e -> case ent_decl e of + Nothing -> Nothing + Just (AST.EntityDec id _) -> Just id + getLibraryUnits :: (HsFunction, FuncData) -- | A function from the session -> [AST.LibraryUnit] -- | The library units it generates getLibraryUnits (hsfunc, fdata) = - case entity fdata of + case funcEntity fdata of Nothing -> [] Just ent -> case ent_decl ent of Nothing -> [] Just decl -> [AST.LUEntity decl] + ++ + case funcArch fdata of + Nothing -> [] + Just arch -> [AST.LUArch arch] -- | The VHDL Bit type bit_ty :: AST.TypeMark bit_ty = AST.unsafeVHDLBasicId "Bit" +-- | The VHDL std_logic +std_logic_ty :: AST.TypeMark +std_logic_ty = AST.unsafeVHDLBasicId "std_logic" + -- Translate a Haskell type to a VHDL type vhdl_ty :: Type.Type -> AST.TypeMark vhdl_ty ty = Maybe.fromMaybe