X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=d2e93897811d0bbb13897b6de2d8758afd20a816;hb=23f93793c5f5f44f1443493c171a0b98295a1651;hp=4ab3be33ec2ba1a9a4647d62703e0efb801c811d;hpb=383e69a4f5ec0b3aa7aa667a0adaf5655a67eee7;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 4ab3be3..d2e9389 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -21,18 +21,16 @@ import FlattenTypes
 import TranslatorTypes
 import Pretty
 
-getDesignFile :: VHDLState AST.DesignFile
-getDesignFile = do
+getDesignFiles :: VHDLState [AST.DesignFile]
+getDesignFiles = do
   -- Extract the library units generated from all the functions in the
   -- session.
   funcs <- getFuncs
-  let units = concat $ map getLibraryUnits funcs
+  let units = Maybe.mapMaybe getLibraryUnits funcs
   let context = [
         AST.Library $ mkVHDLId "IEEE",
         AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
-  return $ AST.DesignFile 
-    context
-    units
+  return $ map (\(ent, arch) -> AST.DesignFile context [ent, arch]) units
   
 -- | Create an entity for a given function
 createEntity ::
@@ -277,18 +275,19 @@ getEntityId fdata =
 
 getLibraryUnits ::
   (HsFunction, FuncData)      -- | A function from the session
-  -> [AST.LibraryUnit]        -- | The library units it generates
+  -> Maybe (AST.LibraryUnit, AST.LibraryUnit) -- | The entity and architecture for the function
 
 getLibraryUnits (hsfunc, fdata) =
   case funcEntity fdata of 
-    Nothing -> []
-    Just ent -> case ent_decl ent of
-      Nothing -> []
-      Just decl -> [AST.LUEntity decl]
-  ++
-  case funcArch fdata of
-    Nothing -> []
-    Just arch -> [AST.LUArch arch]
+    Nothing -> Nothing
+    Just ent -> 
+      case ent_decl ent of
+      Nothing -> Nothing
+      Just decl ->
+        case funcArch fdata of
+          Nothing -> Nothing
+          Just arch ->
+            Just (AST.LUEntity decl, AST.LUArch arch)
 
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark
@@ -330,4 +329,4 @@ mkVHDLId s =
   AST.unsafeVHDLBasicId s'
   where
     -- Strip invalid characters.
-    s' = filter (`elem` ['a'..'z'] ++ ['0'..'9'] ++ ['_']) s
+    s' = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.") s