X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=c952dddf5e2f6a9485e2fdf076a1a0bd6eb057d2;hb=5d228d03054226ebb6e9b9194c180e94a038a81c;hp=572e221b4abb120e94d4871489e5f94b92f1be81;hpb=2fc713015ccdabfb4f979546c3ecd0dd40329bb8;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 572e221..c952ddd 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -375,6 +375,7 @@ mk_fsvec_ty ty args = do
   let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
   let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
   let ty_dec = AST.TypeDec ty_id ty_def
+  -- TODO: Check name uniqueness
   State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
   return ty_id