X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=c646f8b52858f210ea7b69fd816c082c8a03c9a4;hb=969b7ddd86b69d2fc61b101961affcca0364749c;hp=80b069be1dca016621384dbda3c91507a991d8f7;hpb=f55d4e8e7642bd05d44334b83b78850eb5d21df2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/VHDL.hs b/VHDL.hs index 80b069b..c646f8b 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -3,100 +3,162 @@ -- module VHDL where -import qualified Data.Foldable as Foldable +-- Standard modules +import qualified Data.List as List +import qualified Data.Map as Map import qualified Maybe import qualified Control.Monad as Monad +import qualified Control.Arrow as Arrow +import qualified Control.Monad.Trans.State as State +import qualified Data.Monoid as Monoid +import Data.Accessor +import Debug.Trace -import qualified Type -import qualified TysWiredIn +-- ForSyDe +import qualified ForSyDe.Backend.VHDL.AST as AST + +-- GHC API +import CoreSyn +--import qualified Type import qualified Name +import qualified Var +import qualified Id +import qualified IdInfo import qualified TyCon +import qualified DataCon +--import qualified CoreSubst +import qualified CoreUtils import Outputable ( showSDoc, ppr ) -import qualified ForSyDe.Backend.VHDL.AST as AST - +-- Local imports import VHDLTypes -import Flatten -import FlattenTypes -import TranslatorTypes +import VHDLTools import Pretty +import CoreTools +import Constants +import Generate + +createDesignFiles :: + [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)] + -> [(AST.VHDLId, AST.DesignFile)] -getDesignFiles :: VHDLState [AST.DesignFile] -getDesignFiles = do - -- Extract the library units generated from all the functions in the - -- session. - funcs <- getFuncs - let units = Maybe.mapMaybe getLibraryUnits funcs - let context = [ - AST.Library $ mkVHDLId "IEEE", - AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All] - return $ map (\(ent, arch) -> AST.DesignFile context [ent, arch]) units +createDesignFiles binds = + (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body]) : + map (Arrow.second $ AST.DesignFile full_context) units + where + init_session = VHDLState Map.empty Map.empty Map.empty Map.empty + (units, final_session) = + State.runState (createLibraryUnits binds) init_session + tyfun_decls = map snd $ Map.elems (final_session ^.vsTypeFuns) + ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes) + vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes)) + tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def + tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing) + tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range) + ieee_context = [ + AST.Library $ mkVHDLBasicId "IEEE", + mkUseAll ["IEEE", "std_logic_1164"], + mkUseAll ["IEEE", "numeric_std"] + ] + full_context = + mkUseAll ["work", "types"] + : (mkUseAll ["work"] + : ieee_context) + type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs) + type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls + subProgSpecs = map subProgSpec tyfun_decls + subProgSpec = \(AST.SubProgBody spec _ _) -> AST.PDISS spec + mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem + mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def + mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def + +-- Create a use foo.bar.all statement. Takes a list of components in the used +-- name. Must contain at least two components +mkUseAll :: [String] -> AST.ContextItem +mkUseAll ss = + AST.Use $ from AST.:.: AST.All + where + base_prefix = (AST.NSimple $ mkVHDLBasicId $ head ss) + from = foldl select base_prefix (tail ss) + select prefix s = AST.NSelected $ prefix AST.:.: (AST.SSimple $ mkVHDLBasicId s) + +createLibraryUnits :: + [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)] + -> VHDLSession [(AST.VHDLId, [AST.LibraryUnit])] + +createLibraryUnits binds = do + entities <- Monad.mapM createEntity binds + archs <- Monad.mapM createArchitecture binds + return $ zipWith + (\ent arch -> + let AST.EntityDec id _ = ent in + (id, [AST.LUEntity ent, AST.LUArch arch]) + ) + entities archs + -- | Create an entity for a given function createEntity :: - HsFunction -- | The function signature - -> FuncData -- | The function data collected so far - -> VHDLState () - -createEntity hsfunc fdata = - let func = flatFunc fdata in - case func of - -- Skip (builtin) functions without a FlatFunction - Nothing -> do return () - -- Create an entity for all other functions - Just flatfunc -> - - let - sigs = flat_sigs flatfunc - args = flat_args flatfunc - res = flat_res flatfunc - args' = map (fmap (mkMap sigs)) args - res' = fmap (mkMap sigs) res - ent_decl' = createEntityAST hsfunc args' res' - AST.EntityDec entity_id _ = ent_decl' - entity' = Entity entity_id args' res' (Just ent_decl') - in - setEntity hsfunc entity' + (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- | The function + -> VHDLSession AST.EntityDec -- | The resulting entity + +createEntity (fname, expr) = do + -- Strip off lambda's, these will be arguments + let (args, letexpr) = CoreSyn.collectBinders expr + args' <- Monad.mapM mkMap args + -- There must be a let at top level + let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr + res' <- mkMap res + let vhdl_id = mkVHDLBasicId $ varToString fname ++ "_" ++ varToStringUniq fname + let ent_decl' = createEntityAST vhdl_id args' res' + let AST.EntityDec entity_id _ = ent_decl' + let signature = Entity entity_id args' res' + modA vsSignatures (Map.insert fname signature) + return ent_decl' where - mkMap :: Eq id => [(id, SignalInfo)] -> id -> Maybe (AST.VHDLId, AST.TypeMark) - mkMap sigmap id = - if isPortSigUse $ sigUse info - then - Just (mkVHDLId nm, vhdl_ty ty) - else - Nothing - where - info = Maybe.fromMaybe - (error $ "Signal not found in the name map? This should not happen!") - (lookup id sigmap) - nm = Maybe.fromMaybe - (error $ "Signal not named? This should not happen!") - (sigName info) - ty = sigTy info + mkMap :: + --[(SignalId, SignalInfo)] + CoreSyn.CoreBndr + -> VHDLSession VHDLSignalMapElement + -- We only need the vsTypes element from the state + mkMap = (\bndr -> + let + --info = Maybe.fromMaybe + -- (error $ "Signal not found in the name map? This should not happen!") + -- (lookup id sigmap) + -- Assume the bndr has a valid VHDL id already + id = varToVHDLId bndr + ty = Var.varType bndr + in + if True -- isPortSigUse $ sigUse info + then do + type_mark <- vhdl_ty ty + return $ Just (id, type_mark) + else + return $ Nothing + ) -- | Create the VHDL AST for an entity createEntityAST :: - HsFunction -- | The signature of the function we're working with - -> [VHDLSignalMap] -- | The entity's arguments - -> VHDLSignalMap -- | The entity's result - -> AST.EntityDec -- | The entity with the ent_decl filled in as well + AST.VHDLId -- | The name of the function + -> [VHDLSignalMapElement] -- | The entity's arguments + -> VHDLSignalMapElement -- | The entity's result + -> AST.EntityDec -- | The entity with the ent_decl filled in as well -createEntityAST hsfunc args res = +createEntityAST vhdl_id args res = AST.EntityDec vhdl_id ports where - vhdl_id = mkEntityId hsfunc - ports = concatMap (mapToPorts AST.In) args - ++ mapToPorts AST.Out res - ++ clk_port - mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] - mapToPorts mode m = - Maybe.catMaybes $ map (mkIfaceSigDec mode) (Foldable.toList m) + -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids. + ports = Maybe.catMaybes $ + map (mkIfaceSigDec AST.In) args + ++ [mkIfaceSigDec AST.Out res] + ++ [clk_port] -- Add a clk port if we have state - clk_port = if hasState hsfunc + clk_port = if True -- hasState hsfunc then - [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty] + Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In std_logicTM else - [] + Nothing -- | Create a port declaration mkIfaceSigDec :: @@ -107,41 +169,47 @@ mkIfaceSigDec :: mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty mkIfaceSigDec _ Nothing = Nothing +{- -- | Generate a VHDL entity name for the given hsfunc mkEntityId hsfunc = -- TODO: This doesn't work for functions with multiple signatures! - mkVHDLId $ hsFuncName hsfunc + -- Use a Basic Id, since using extended id's for entities throws off + -- precision and causes problems when generating filenames. + mkVHDLBasicId $ hsFuncName hsfunc +-} -- | Create an architecture for a given function createArchitecture :: - HsFunction -- | The function signature - -> FuncData -- | The function data collected so far - -> VHDLState () - -createArchitecture hsfunc fdata = - let func = flatFunc fdata in - case func of - -- Skip (builtin) functions without a FlatFunction - Nothing -> do return () - -- Create an architecture for all other functions - Just flatfunc -> do - let sigs = flat_sigs flatfunc - let args = flat_args flatfunc - let res = flat_res flatfunc - let defs = flat_defs flatfunc - let entity_id = Maybe.fromMaybe - (error $ "Building architecture without an entity? This should not happen!") - (getEntityId fdata) - -- Create signal declarations for all signals that are not in args and - -- res - let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs - -- Create concurrent statements for all signal definitions - statements <- mapM (mkConcSm sigs) defs - let procs = map mkStateProcSm (makeStatePairs flatfunc) - let procs' = map AST.CSPSm procs - let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs') - setArchitecture hsfunc arch + (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The function + -> VHDLSession AST.ArchBody -- ^ The architecture for this function + +createArchitecture (fname, expr) = do + signaturemap <- getA vsSignatures + let signature = Maybe.fromMaybe + (error $ "Generating architecture for function " ++ (pprString fname) ++ "without signature? This should not happen!") + (Map.lookup fname signaturemap) + let entity_id = ent_id signature + -- Strip off lambda's, these will be arguments + let (args, letexpr) = CoreSyn.collectBinders expr + -- There must be a let at top level + let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr + + -- Create signal declarations for all binders in the let expression, except + -- for the output port (that will already have an output port declared in + -- the entity). + sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds) + let sig_decs = Maybe.catMaybes $ sig_dec_maybes + + statementss <- Monad.mapM mkConcSm binds + let statements = concat statementss + return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs') + where + procs = [] --map mkStateProcSm [] -- (makeStatePairs flatfunc) + procs' = map AST.CSPSm procs + -- mkSigDec only uses vsTypes from the state + mkSigDec' = mkSigDec +{- -- | Looks up all pairs of old state, new state signals, together with -- the state id they represent. makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)] @@ -161,187 +229,81 @@ mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm mkStateProcSm (num, old, new) = AST.ProcSm label [clk] [statement] where - label = mkVHDLId $ "state_" ++ (show num) - clk = mkVHDLId "clk" - rising_edge = AST.NSimple $ mkVHDLId "rising_edge" + label = mkVHDLExtId $ "state_" ++ (show num) + clk = mkVHDLExtId "clk" + rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge" wform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple $ getSignalId new) Nothing] assign = AST.SigAssign (AST.NSimple $ getSignalId old) wform rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)] statement = AST.IfSm rising_edge_clk [assign] [] Nothing -mkSigDec :: SignalInfo -> Maybe AST.SigDec -mkSigDec info = - let use = sigUse info in - if isInternalSigUse use || isStateSigUse use then - Just $ AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing - else - Nothing - where - ty = sigTy info - -- | Creates a VHDL Id from a named SignalInfo. Errors out if the SignalInfo -- is not named. getSignalId :: SignalInfo -> AST.VHDLId getSignalId info = - mkVHDLId $ Maybe.fromMaybe - (error $ "Unnamed signal? This should not happen!") - (sigName info) + mkVHDLExtId $ Maybe.fromMaybe + (error $ "Unnamed signal? This should not happen!") + (sigName info) +-} + +mkSigDec :: CoreSyn.CoreBndr -> VHDLSession (Maybe AST.SigDec) +mkSigDec bndr = + if True then do --isInternalSigUse use || isStateSigUse use then do + type_mark <- vhdl_ty $ Var.varType bndr + return $ Just (AST.SigDec (varToVHDLId bndr) type_mark Nothing) + else + return Nothing --- | Transforms a signal definition into a VHDL concurrent statement +-- | Transforms a core binding into a VHDL concurrent statement mkConcSm :: - [(SignalId, SignalInfo)] -- | The signals in the current architecture - -> SigDef -- | The signal definition - -> VHDLState AST.ConcSm -- | The corresponding VHDL component instantiation. - -mkConcSm sigs (FApp hsfunc args res) = do - fdata_maybe <- getFunc hsfunc - let fdata = Maybe.fromMaybe - (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' that is not in the session? This should not happen!") - fdata_maybe - let entity = Maybe.fromMaybe - (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' without entity declaration? This should not happen!") - (funcEntity fdata) - let entity_id = ent_id entity - label <- uniqueName (AST.fromVHDLId entity_id) - let portmaps = mkAssocElems sigs args res entity - return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps) - -mkConcSm sigs (UncondDef src dst) = do - let src_expr = vhdl_expr src - let src_wform = AST.Wform [AST.WformElem src_expr Nothing] - let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst) - let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing) - return $ AST.CSSASm assign - where - vhdl_expr (Left id) = mkIdExpr sigs id - vhdl_expr (Right expr) = - case expr of - (EqLit id lit) -> - (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit) - (Literal lit) -> - AST.PrimLit lit - (Eq a b) -> - (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b) - -mkConcSm sigs (CondDef cond true false dst) = do - let cond_expr = mkIdExpr sigs cond - let true_expr = mkIdExpr sigs true - let false_expr = mkIdExpr sigs false - let false_wform = AST.Wform [AST.WformElem false_expr Nothing] - let true_wform = AST.Wform [AST.WformElem true_expr Nothing] - let whenelse = AST.WhenElse true_wform cond_expr - let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst) - let assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing) - return $ AST.CSSASm assign - --- | Turn a SignalId into a VHDL Expr -mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr -mkIdExpr sigs id = - let src_name = AST.NSimple (getSignalId $ signalInfo sigs id) in - AST.PrimName src_name - -mkAssocElems :: - [(SignalId, SignalInfo)] -- | The signals in the current architecture - -> [SignalMap] -- | The signals that are applied to function - -> SignalMap -- | the signals in which to store the function result - -> Entity -- | The entity to map against. - -> [AST.AssocElem] -- | The resulting port maps - -mkAssocElems sigmap args res entity = - -- Create the actual AssocElems - Maybe.catMaybes $ zipWith mkAssocElem ports sigs - where - -- Turn the ports and signals from a map into a flat list. This works, - -- since the maps must have an identical form by definition. TODO: Check - -- the similar form? - arg_ports = concat (map Foldable.toList (ent_args entity)) - res_ports = Foldable.toList (ent_res entity) - arg_sigs = (concat (map Foldable.toList args)) - res_sigs = Foldable.toList res - -- Extract the id part from the (id, type) tuple - ports = (map (fmap fst) (arg_ports ++ res_ports)) - -- Translate signal numbers into names - sigs = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs)) - --- | Look up a signal in the signal name map -lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String -lookupSigName sigs sig = name - where - info = Maybe.fromMaybe - (error $ "Unknown signal " ++ (show sig) ++ " used? This should not happen!") - (lookup sig sigs) - name = Maybe.fromMaybe - (error $ "Unnamed signal " ++ (show sig) ++ " used? This should not happen!") - (sigName info) - --- | Create an VHDL port -> signal association -mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem -mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) -mkAssocElem Nothing _ = Nothing - --- | Extracts the generated entity id from the given funcdata -getEntityId :: FuncData -> Maybe AST.VHDLId -getEntityId fdata = - case funcEntity fdata of - Nothing -> Nothing - Just e -> case ent_decl e of - Nothing -> Nothing - Just (AST.EntityDec id _) -> Just id - -getLibraryUnits :: - (HsFunction, FuncData) -- | A function from the session - -> Maybe (AST.LibraryUnit, AST.LibraryUnit) -- | The entity and architecture for the function - -getLibraryUnits (hsfunc, fdata) = - case funcEntity fdata of - Nothing -> Nothing - Just ent -> - case ent_decl ent of - Nothing -> Nothing - Just decl -> - case funcArch fdata of - Nothing -> Nothing - Just arch -> - Just (AST.LUEntity decl, AST.LUArch arch) - --- | The VHDL Bit type -bit_ty :: AST.TypeMark -bit_ty = AST.unsafeVHDLBasicId "Bit" - --- | The VHDL Boolean type -bool_ty :: AST.TypeMark -bool_ty = AST.unsafeVHDLBasicId "Boolean" - --- | The VHDL std_logic -std_logic_ty :: AST.TypeMark -std_logic_ty = AST.unsafeVHDLBasicId "std_logic" - --- Translate a Haskell type to a VHDL type -vhdl_ty :: Type.Type -> AST.TypeMark -vhdl_ty ty = Maybe.fromMaybe - (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty)) - (vhdl_ty_maybe ty) - --- Translate a Haskell type to a VHDL type -vhdl_ty_maybe :: Type.Type -> Maybe AST.TypeMark -vhdl_ty_maybe ty = - if Type.coreEqType ty TysWiredIn.boolTy - then - Just bool_ty - else - case Type.splitTyConApp_maybe ty of - Just (tycon, args) -> - let name = TyCon.tyConName tycon in - -- TODO: Do something more robust than string matching - case Name.getOccString name of - "Bit" -> Just std_logic_ty - otherwise -> Nothing - otherwise -> Nothing - --- Shortcut -mkVHDLId :: String -> AST.VHDLId -mkVHDLId s = - AST.unsafeVHDLBasicId s' - where - -- Strip invalid characters. - s' = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.") s + (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process + -> VHDLSession [AST.ConcSm] -- ^ The corresponding VHDL component instantiations. + + +-- Ignore Cast expressions, they should not longer have any meaning as long as +-- the type works out. +mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr) + +-- For simple a = b assignments, just generate an unconditional signal +-- assignment. This should only happen for dataconstructors without arguments. +-- TODO: Integrate this with the below code for application (essentially this +-- is an application without arguments) +mkConcSm (bndr, Var v) = return $ [mkUncondAssign (Left bndr) (varToVHDLExpr v)] + +mkConcSm (bndr, app@(CoreSyn.App _ _))= do + let (CoreSyn.Var f, args) = CoreSyn.collectArgs app + let valargs' = filter isValArg args + let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs' + genApplication (Left bndr) f (map Left valargs) + +-- A single alt case must be a selector. This means thee scrutinee is a simple +-- variable, the alternative is a dataalt with a single non-wild binder that +-- is also returned. +mkConcSm (bndr, expr@(Case (Var scrut) b ty [alt])) = + case alt of + (DataAlt dc, bndrs, (Var sel_bndr)) -> do + case List.elemIndex sel_bndr bndrs of + Just i -> do + labels <- getFieldLabels (Id.idType scrut) + let label = labels!!i + let sel_name = mkSelectedName (varToVHDLName scrut) label + let sel_expr = AST.PrimName sel_name + return [mkUncondAssign (Left bndr) sel_expr] + Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr) + + _ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr) + +-- Multiple case alt are be conditional assignments and have only wild +-- binders in the alts and only variables in the case values and a variable +-- for a scrutinee. We check the constructor of the second alt, since the +-- first is the default case, if there is any. +mkConcSm (bndr, (Case (Var scrut) b ty [(_, _, Var false), (con, _, Var true)])) = + let + cond_expr = (varToVHDLExpr scrut) AST.:=: (altconToVHDLExpr con) + true_expr = (varToVHDLExpr true) + false_expr = (varToVHDLExpr false) + in + return [mkCondAssign (Left bndr) cond_expr true_expr false_expr] +mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives" +mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee" +mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr