X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=b6264dcf603266807297718c8e318a8e47dee878;hb=30414e977c5c4ba3c16441a281601c7c68f0fb6e;hp=f9367ef66da93f5a7217a7701d8fe40d1b296dee;hpb=6fffdcf32a54a6372442d22a87537ee9733073ad;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/VHDL.hs b/VHDL.hs index f9367ef..b6264dc 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -12,6 +12,7 @@ import qualified Control.Arrow as Arrow import qualified Control.Monad.Trans.State as State import qualified Data.Monoid as Monoid import Data.Accessor +import Debug.Trace -- ForSyDe import qualified ForSyDe.Backend.VHDL.AST as AST @@ -36,7 +37,6 @@ import Pretty import CoreTools import Constants import Generate -import GlobalNameTable createDesignFiles :: [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)] @@ -50,7 +50,7 @@ createDesignFiles binds = init_session = VHDLState Map.empty Map.empty Map.empty Map.empty (units, final_session) = State.runState (createLibraryUnits binds) init_session - tyfun_decls = Map.elems (final_session ^.vsTypeFuns) + tyfun_decls = map snd $ Map.elems (final_session ^.vsTypeFuns) ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes) vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes)) tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def @@ -66,9 +66,9 @@ createDesignFiles binds = : (mkUseAll ["work"] : ieee_context) type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs) - type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls) - subProgSpecs = concat (map subProgSpec tyfun_decls) - subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec) + type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls + subProgSpecs = map subProgSpec tyfun_decls + subProgSpec = \(AST.SubProgBody spec _ _) -> AST.PDISS spec mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def @@ -119,7 +119,7 @@ createEntity (fname, expr) = do mkMap :: --[(SignalId, SignalInfo)] CoreSyn.CoreBndr - -> VHDLSession VHDLSignalMapElement + -> VHDLSession Port -- We only need the vsTypes element from the state mkMap = (\bndr -> let @@ -129,45 +129,35 @@ createEntity (fname, expr) = do -- Assume the bndr has a valid VHDL id already id = varToVHDLId bndr ty = Var.varType bndr - in - if True -- isPortSigUse $ sigUse info - then do - type_mark <- vhdl_ty ty - return $ Just (id, type_mark) - else - return $ Nothing - ) + in do + type_mark <- vhdl_ty ty + return (id, type_mark) + ) -- | Create the VHDL AST for an entity createEntityAST :: AST.VHDLId -- | The name of the function - -> [VHDLSignalMapElement] -- | The entity's arguments - -> VHDLSignalMapElement -- | The entity's result + -> [Port] -- | The entity's arguments + -> Port -- | The entity's result -> AST.EntityDec -- | The entity with the ent_decl filled in as well createEntityAST vhdl_id args res = AST.EntityDec vhdl_id ports where -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids. - ports = Maybe.catMaybes $ - map (mkIfaceSigDec AST.In) args + ports = map (mkIfaceSigDec AST.In) args ++ [mkIfaceSigDec AST.Out res] ++ [clk_port] -- Add a clk port if we have state - clk_port = if True -- hasState hsfunc - then - Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In std_logicTM - else - Nothing + clk_port = AST.IfaceSigDec (mkVHDLExtId "clk") AST.In std_logicTM -- | Create a port declaration mkIfaceSigDec :: AST.Mode -- | The mode for the port (In / Out) - -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port - -> Maybe AST.IfaceSigDec -- | The resulting port declaration + -> (AST.VHDLId, AST.TypeMark) -- | The id and type for the port + -> AST.IfaceSigDec -- | The resulting port declaration -mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty -mkIfaceSigDec _ Nothing = Nothing +mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty {- -- | Generate a VHDL entity name for the given hsfunc @@ -274,67 +264,7 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do let (CoreSyn.Var f, args) = CoreSyn.collectArgs app let valargs' = filter isValArg args let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs' - case Var.globalIdVarDetails f of - IdInfo.DataConWorkId dc -> - -- It's a datacon. Create a record from its arguments. - -- First, filter out type args. TODO: Is this the best way to do this? - -- The types should already have been taken into acocunt when creating - -- the signal, so this should probably work... - --let valargs = filter isValArg args in - if all is_var valargs then do - labels <- getFieldLabels (CoreUtils.exprType app) - return $ zipWith mkassign labels valargs - else - error $ "VHDL.mkConcSm Not in normal form: One ore more complex arguments: " ++ pprString args - where - mkassign :: AST.VHDLId -> CoreExpr -> AST.ConcSm - mkassign label (Var arg) = - let sel_name = mkSelectedName bndr label in - mkUncondAssign (Right sel_name) (varToVHDLExpr arg) - IdInfo.VanillaGlobal -> do - -- It's a global value imported from elsewhere. These can be builtin - -- functions. - signatures <- getA vsSignatures - case (Map.lookup (varToString f) globalNameTable) of - Just (arg_count, builder) -> - if length valargs == arg_count then - case builder of - Left funBuilder -> do - let sigs = map (varToVHDLExpr.exprToVar) valargs - func <- funBuilder sigs - let src_wform = AST.Wform [AST.WformElem func Nothing] - let dst_name = AST.NSimple (mkVHDLExtId (varToString bndr)) - let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing) - return [AST.CSSASm assign] - Right genBuilder -> do - let sigs = map exprToVar valargs - let signature = Maybe.fromMaybe - (error $ "Using function '" ++ (varToString (head sigs)) ++ "' without signature? This should not happen!") - (Map.lookup (head sigs) signatures) - let arg = tail sigs - genSm <- genBuilder signature (arg ++ [bndr]) - return [AST.CSGSm genSm] - else - error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs - Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f - IdInfo.NotGlobalId -> do - signatures <- getA vsSignatures - -- This is a local id, so it should be a function whose definition we - -- have and which can be turned into a component instantiation. - let - signature = Maybe.fromMaybe - (error $ "Using function '" ++ (varToString f) ++ "' without signature? This should not happen!") - (Map.lookup f signatures) - entity_id = ent_id signature - label = "comp_ins_" ++ varToString bndr - -- Add a clk port if we have state - --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk" - clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk" - --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else []) - portmaps = clk_port : mkAssocElems args bndr signature - in - return [mkComponentInst label entity_id portmaps] - details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details + genApplication (Left bndr) f (map Left valargs) -- A single alt case must be a selector. This means thee scrutinee is a simple -- variable, the alternative is a dataalt with a single non-wild binder that @@ -346,7 +276,7 @@ mkConcSm (bndr, expr@(Case (Var scrut) b ty [alt])) = Just i -> do labels <- getFieldLabels (Id.idType scrut) let label = labels!!i - let sel_name = mkSelectedName scrut label + let sel_name = mkSelectedName (varToVHDLName scrut) label let sel_expr = AST.PrimName sel_name return [mkUncondAssign (Left bndr) sel_expr] Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)