X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=b448672131c980bbe0df173fe86938235ce50ea7;hb=57a2771de1d155d9c382614531f88882ed74325b;hp=80b069be1dca016621384dbda3c91507a991d8f7;hpb=f55d4e8e7642bd05d44334b83b78850eb5d21df2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 80b069b..b448672 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -203,7 +203,9 @@ mkConcSm sigs (FApp hsfunc args res) = do
         (funcEntity fdata)
   let entity_id = ent_id entity
   label <- uniqueName (AST.fromVHDLId entity_id)
-  let portmaps = mkAssocElems sigs args res entity
+  -- Add a clk port if we have state
+  let clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk"
+  let portmaps = mkAssocElems sigs args res entity ++ (if hasState hsfunc then [clk_port] else [])
   return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
 
 mkConcSm sigs (UncondDef src dst) = do