X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=b2d5b30e448964d450934b88a343d309a44c8b09;hb=c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87;hp=eb454203ebeda699ebcc9c595f4a6f395dbdfee7;hpb=019e55a763768d778d0e62b4dc5e49f3c7e06a0f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/VHDL.hs b/VHDL.hs index eb45420..b2d5b30 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -264,6 +264,11 @@ mkConcSm :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations. + +-- Ignore Cast expressions, they should not longer have any meaning as long as +-- the type works out. +mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr) + mkConcSm (bndr, app@(CoreSyn.App _ _))= do let (CoreSyn.Var f, args) = CoreSyn.collectArgs app let valargs' = filter isValArg args