X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=ae72368f4f9fd0b6eccbe9f20f7836ef0d4da733;hb=527a6aa73e730b0837d9cec13554ceaacb0a2fca;hp=c1b42b3bc89a9b2764ff60626957a036b9242649;hpb=38ac166769b7280fcb9e63f6fda3955d9b58ce11;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index c1b42b3..ae72368 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -369,7 +369,8 @@ mk_fsvec_ty ty args = do
   -- Assume there are two type arguments
   let [len, el_ty] = args 
   -- TODO: Find actual number
-  let ty_id = mkVHDLId ("vector_" ++ (show len))
+  -- Construct the type id, but filter out dots (since these are not allowed).
+  let ty_id = mkVHDLId $ filter (/='.') ("vector_" ++ (show len))
   -- TODO: Use el_ty
   let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
   let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty