X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=ab7ee22596dbb4cbb9220e1ec78646c4588145df;hb=d440d5946729bd07e47ef2f3fed58bbe1284f8fa;hp=76a2552e98c7805ccd74b333b5795ba603b1e1cd;hpb=cfc96ca7a1a615b1e36fbee996631f13f8b494cd;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 76a2552..ab7ee22 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -56,7 +56,7 @@ createDesignFiles binds =
   map (Arrow.second $ AST.DesignFile full_context) units
   
   where
-    init_session = VHDLSession Map.empty Map.empty Map.empty builtin_funcs globalNameTable
+    init_session = VHDLSession Map.empty Map.empty Map.empty Map.empty globalNameTable
     (units, final_session) = 
       State.runState (createLibraryUnits binds) init_session
     tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
@@ -280,20 +280,23 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
           let sel_name = mkSelectedName bndr label in
           mkUncondAssign (Right sel_name) (varToVHDLExpr arg)
     IdInfo.VanillaGlobal -> do
-      -- It's a global value imported from elsewhere. These can be builting
+      -- It's a global value imported from elsewhere. These can be builtin
       -- functions.
       funSignatures <- getA vsNameTable
       case (Map.lookup (bndrToString f) funSignatures) of
-        Just funSignature ->
-          let
-            sigs = map (bndrToString.varBndr) args
-            sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
-            func = (snd funSignature) sigsNames
-            src_wform = AST.Wform [AST.WformElem func Nothing]
-            dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
-            assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
-          in
-            return $ AST.CSSASm assign
+        Just (arg_count, builder) ->
+          if length args == arg_count then
+            let
+              sigs = map (bndrToString.varBndr) args
+              sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
+              func = builder sigsNames
+              src_wform = AST.Wform [AST.WformElem func Nothing]
+              dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
+              assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
+            in
+              return $ AST.CSSASm assign
+          else
+            error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString args
         Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
     IdInfo.NotGlobalId -> do
       signatures <- getA vsSignatures
@@ -348,6 +351,7 @@ mkConcSm (bndr, (Case (Var scrut) b ty [(_, _, Var false), (con, _, Var true)]))
     return $ mkCondAssign (Left bndr) cond_expr true_expr false_expr
 mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
 mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
+mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
 
 -- Create an unconditional assignment statement
 mkUncondAssign ::
@@ -698,28 +702,6 @@ bndrToString = OccName.occNameString . Name.nameOccName . Var.varName
 nameToString :: Name.Name -> String
 nameToString = OccName.occNameString . Name.nameOccName
 
--- | A consise representation of a (set of) ports on a builtin function
---type PortMap = HsValueMap (String, AST.TypeMark)
--- | A consise representation of a builtin function
-data BuiltIn = BuiltIn String [(String, AST.TypeMark)] (String, AST.TypeMark)
-
--- | Translate a list of concise representation of builtin functions to a
---   SignatureMap
-mkBuiltins :: [BuiltIn] -> SignatureMap
-mkBuiltins = Map.fromList . map (\(BuiltIn name args res) ->
-    (name,
-     Entity (VHDL.mkVHDLBasicId name) (map toVHDLSignalMapElement args) (toVHDLSignalMapElement res))
-  )
-
-builtin_hsfuncs = Map.keys builtin_funcs
-builtin_funcs = mkBuiltins
-  [ 
-    BuiltIn "hwxor" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty),
-    BuiltIn "hwand" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty),
-    BuiltIn "hwor" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty),
-    BuiltIn "hwnot" [("a", VHDL.bit_ty)] ("o", VHDL.bit_ty)
-  ]
-
 recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
 
 -- | Map a port specification of a builtin function to a VHDL Signal to put in