X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=998efb476669c8518fa2b29dc904e2bd93cfc6c3;hb=a44db062ae75b4fe3ce28368e07323130a14fe58;hp=76cb62f827d87c24faa2e48df4af4f7527566499;hpb=8c52b6cf13be6b0080ce3353bebfd04b18336036;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 76cb62f..998efb4 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -313,7 +313,7 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
                       (Map.lookup (head sigs) signatures)
                 let arg = tail sigs
                 genSm <- genBuilder signature (arg ++ [bndr])  
-                return [AST.CSGSm genSm]
+                return [genSm]
           else
             error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs
         Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
@@ -329,9 +329,9 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
         label = "comp_ins_" ++ varToString bndr
         -- Add a clk port if we have state
         --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
-        clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+        --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
         --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
-        portmaps = clk_port : mkAssocElems args bndr signature
+        portmaps = mkAssocElems args bndr signature
         in
           return [mkComponentInst label entity_id portmaps]
     details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details