X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=92df267811bb480859f5a00712fa670e57e04ea4;hb=fa8761cd4d31ca41f79de1bd0861a1552c9274f8;hp=ecf6406f95e3f3f621b835d74497eb4feb5b2110;hpb=4e34d6b1baa6e0754432254fabc2fa822b755f0b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index ecf6406..92df267 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -624,7 +624,7 @@ mk_vector_ty len el_ty ty = do
   elem_types_map <- getA vsElemTypes
   el_ty_tm <- vhdl_ty el_ty
   let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
-  let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
+  let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
   let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
   case existing_elem_ty of
     Just t -> do
@@ -645,7 +645,8 @@ mk_natural_ty ::
   -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
 mk_natural_ty min_bound max_bound ty = do
   let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
-  let ty_def = AST.SubtypeIn naturalTM (Nothing)
+  let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound))
+  let ty_def = AST.SubtypeIn naturalTM (Just range)
   return (ty_id, ty_def)