X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=8c2fe0315b525a96fa1585b14b11b0b9b9051ef1;hb=472a96af53dd624ba526ab86f250ac8f88a152ef;hp=192714778d5605c40efd37dc2cc85dc1540890f4;hpb=85ee6f8e10f7dcc73db62a55a07d924bc002f216;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 1927147..8c2fe03 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -4,6 +4,7 @@
 module VHDL where
 
 import Data.Traversable
+import qualified Data.Foldable as Foldable
 import qualified Maybe
 
 import qualified Type
@@ -32,19 +33,19 @@ createEntity hsfunc fdata =
     Just flatfunc ->
       
       let 
-        s       = sigs flatfunc
-        a       = args flatfunc
-        r       = res  flatfunc
-        args'   = map (fmap (mkMap s)) a
-        res'    = fmap (mkMap s) r
+        sigs    = flat_sigs flatfunc
+        args    = flat_args flatfunc
+        res     = flat_res  flatfunc
+        args'   = map (fmap (mkMap sigs)) args
+        res'    = fmap (mkMap sigs) res
         ent_decl' = createEntityAST hsfunc args' res'
         entity' = Entity args' res' (Just ent_decl')
       in
-        fdata { entity = Just entity' }
+        fdata { funcEntity = Just entity' }
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> AST.VHDLId
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      mkVHDLId nm
+      (mkVHDLId nm, vhdl_ty ty)
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
@@ -52,6 +53,7 @@ createEntity hsfunc fdata =
         nm = Maybe.fromMaybe
           (error $ "Signal not named? This should not happen!")
           (sigName info)
+        ty = sigTy info
 
 -- | Create the VHDL AST for an entity
 createEntityAST ::
@@ -64,23 +66,84 @@ createEntityAST hsfunc args res =
   AST.EntityDec vhdl_id ports
   where
     vhdl_id = mkEntityId hsfunc
-    ports = []
+    ports = concatMap (mapToPorts AST.In) args
+            ++ mapToPorts AST.Out res
+    mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] 
+    mapToPorts mode m =
+      map (mkIfaceSigDec mode) (Foldable.toList m)
+
+-- | Create a port declaration
+mkIfaceSigDec ::
+  AST.Mode                         -- | The mode for the port (In / Out)
+  -> (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
+  -> AST.IfaceSigDec               -- | The resulting port declaration
+
+mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
 
 -- | Generate a VHDL entity name for the given hsfunc
 mkEntityId hsfunc =
   -- TODO: This doesn't work for functions with multiple signatures!
   mkVHDLId $ hsFuncName hsfunc
 
+-- | Create an architecture for a given function
+createArchitecture ::
+  HsFunction        -- | The function signature
+  -> FuncData       -- | The function data collected so far
+  -> FuncData       -- | The modified function data
+
+createArchitecture hsfunc fdata = 
+  let func = flatFunc fdata in
+  case func of
+    -- Skip (builtin) functions without a FlatFunction
+    Nothing -> fdata
+    -- Create an architecture for all other functions
+    Just flatfunc ->
+      let 
+        sigs      = flat_sigs flatfunc
+        args      = flat_args flatfunc
+        res       = flat_res  flatfunc
+        entity_id = Maybe.fromMaybe
+                      (error $ "Building architecture without an entity? This should not happen!")
+                      (getEntityId fdata)
+        -- Create signal declarations for all signals that are not in args and
+        -- res
+        sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ]
+        arch     = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) []
+      in
+        fdata { funcArch = Just arch }
+
+mkSigDec :: SignalInfo -> AST.SigDec
+mkSigDec info =
+    AST.SigDec (mkVHDLId name) (vhdl_ty ty) Nothing
+  where
+    name = Maybe.fromMaybe
+      (error $ "Unnamed signal? This should not happen!")
+      (sigName info)
+    ty = sigTy info
+    
+-- | Extracts the generated entity id from the given funcdata
+getEntityId :: FuncData -> Maybe AST.VHDLId
+getEntityId fdata =
+  case funcEntity fdata of
+    Nothing -> Nothing
+    Just e  -> case ent_decl e of
+      Nothing -> Nothing
+      Just (AST.EntityDec id _) -> Just id
+
 getLibraryUnits ::
   (HsFunction, FuncData)      -- | A function from the session
   -> [AST.LibraryUnit]        -- | The library units it generates
 
 getLibraryUnits (hsfunc, fdata) =
-  case entity fdata of 
+  case funcEntity fdata of 
     Nothing -> []
     Just ent -> case ent_decl ent of
       Nothing -> []
       Just decl -> [AST.LUEntity decl]
+  ++
+  case funcArch fdata of
+    Nothing -> []
+    Just arch -> [AST.LUArch arch]
 
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark