X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=8bc67a39dba4cdc9592e35fd17724c27e2871246;hb=1476a5bd6c7c174ffbd39a178caa9701bdd39ac1;hp=c646f8b52858f210ea7b69fd816c082c8a03c9a4;hpb=969b7ddd86b69d2fc61b101961affcca0364749c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index c646f8b..8bc67a3 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -119,7 +119,7 @@ createEntity (fname, expr) = do
     mkMap ::
       --[(SignalId, SignalInfo)] 
       CoreSyn.CoreBndr 
-      -> VHDLSession VHDLSignalMapElement
+      -> VHDLSession Port
     -- We only need the vsTypes element from the state
     mkMap = (\bndr ->
       let
@@ -129,45 +129,35 @@ createEntity (fname, expr) = do
         --  Assume the bndr has a valid VHDL id already
         id = varToVHDLId bndr
         ty = Var.varType bndr
-      in
-        if True -- isPortSigUse $ sigUse info
-          then do
-            type_mark <- vhdl_ty ty
-            return $ Just (id, type_mark)
-          else
-            return $ Nothing
-       )
+      in do
+        type_mark <- vhdl_ty ty
+        return (id, type_mark)
+     )
 
   -- | Create the VHDL AST for an entity
 createEntityAST ::
   AST.VHDLId                   -- | The name of the function
-  -> [VHDLSignalMapElement]    -- | The entity's arguments
-  -> VHDLSignalMapElement      -- | The entity's result
+  -> [Port]                    -- | The entity's arguments
+  -> Port                      -- | The entity's result
   -> AST.EntityDec             -- | The entity with the ent_decl filled in as well
 
 createEntityAST vhdl_id args res =
   AST.EntityDec vhdl_id ports
   where
     -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
-    ports = Maybe.catMaybes $ 
-              map (mkIfaceSigDec AST.In) args
+    ports = map (mkIfaceSigDec AST.In) args
               ++ [mkIfaceSigDec AST.Out res]
               ++ [clk_port]
     -- Add a clk port if we have state
-    clk_port = if True -- hasState hsfunc
-      then
-        Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In std_logicTM
-      else
-        Nothing
+    clk_port = AST.IfaceSigDec (mkVHDLExtId "clk") AST.In std_logicTM
 
 -- | Create a port declaration
 mkIfaceSigDec ::
   AST.Mode                         -- | The mode for the port (In / Out)
-  -> Maybe (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
-  -> Maybe AST.IfaceSigDec               -- | The resulting port declaration
+  -> (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
+  -> AST.IfaceSigDec               -- | The resulting port declaration
 
-mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
-mkIfaceSigDec _ Nothing = Nothing
+mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
 
 {-
 -- | Generate a VHDL entity name for the given hsfunc
@@ -272,8 +262,7 @@ mkConcSm (bndr, Var v) = return $ [mkUncondAssign (Left bndr) (varToVHDLExpr v)]
 
 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
   let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
-  let valargs' = filter isValArg args
-  let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs'
+  let valargs = get_val_args (Var.varType f) args
   genApplication (Left bndr) f (map Left valargs)
 
 -- A single alt case must be a selector. This means thee scrutinee is a simple