X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=8bc67a39dba4cdc9592e35fd17724c27e2871246;hb=1476a5bd6c7c174ffbd39a178caa9701bdd39ac1;hp=b6264dcf603266807297718c8e318a8e47dee878;hpb=59b710f483534efd4a293f880235f444a5156451;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index b6264dc..8bc67a3 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -262,8 +262,7 @@ mkConcSm (bndr, Var v) = return $ [mkUncondAssign (Left bndr) (varToVHDLExpr v)]
 
 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
   let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
-  let valargs' = filter isValArg args
-  let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs'
+  let valargs = get_val_args (Var.varType f) args
   genApplication (Left bndr) f (map Left valargs)
 
 -- A single alt case must be a selector. This means thee scrutinee is a simple