X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=8ae351611a6201dfd8a6c7dc7119d916e3961616;hb=6093a850e28df3e081a80a73995e3b7279c106d5;hp=1d605ea7de71b1279ce051e5f675eb1aa7c193c8;hpb=a3ff46ea19a1966c2268fe99df24c15d04abc000;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 1d605ea..8ae3516 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -50,7 +50,8 @@ createDesignFiles flatfuncmap =
     ty_decls = Map.elems (final_session ^. vsTypes)
     ieee_context = [
         AST.Library $ mkVHDLBasicId "IEEE",
-        mkUseAll ["IEEE", "std_logic_1164"]
+        mkUseAll ["IEEE", "std_logic_1164"],
+        mkUseAll ["IEEE", "numeric_std"]
       ]
     full_context =
       mkUseAll ["work", "types"]