X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=84e4e379eabc6dce461728272a96ae0c41056d41;hb=daba7a870fe4808faf6e54b26572a707237ec3c2;hp=ec6e5833490f4080507f9e6908d114964a3c2bdf;hpb=7ee0795d9aa7ca1db317216126706f8fcac62ab6;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index ec6e583..84e4e37 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -199,10 +199,12 @@ createArchitecture (fname, expr) = do
   -- Strip off lambda's, these will be arguments
   let (args, letexpr) = CoreSyn.collectBinders expr
   -- There must be a let at top level 
-  let (CoreSyn.Let (CoreSyn.Rec binds) res) = letexpr
+  let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr
 
-  -- Create signal declarations for all internal and state signals
-  sig_dec_maybes <- mapM (mkSigDec' . fst) binds
+  -- Create signal declarations for all binders in the let expression, except
+  -- for the output port (that will already have an output port declared in
+  -- the entity).
+  sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
   let sig_decs = Maybe.catMaybes $ sig_dec_maybes
 
   statements <- Monad.mapM mkConcSm binds