X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=37bcd74c461a8f4b2b9b57fe2f2d411257f77dca;hb=acb620510e3623e8dfd979a8b732babd19086a9b;hp=b85d6ff0be288e7db0ec57ca886fae79cbc6ec09;hpb=14367b6b9fd0770a78e02fad425daa369df4bec6;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index b85d6ff..37bcd74 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -320,10 +320,14 @@ vhdl_ty_maybe ty =
           let name = TyCon.tyConName tycon in
             -- TODO: Do something more robust than string matching
             case Name.getOccString name of
-              "Bit"      -> Just bit_ty
+              "Bit"      -> Just std_logic_ty
               otherwise  -> Nothing
         otherwise -> Nothing
 
 -- Shortcut
 mkVHDLId :: String -> AST.VHDLId
-mkVHDLId = AST.unsafeVHDLBasicId
+mkVHDLId s = 
+  AST.unsafeVHDLBasicId s'
+  where
+    -- Strip invalid characters.
+    s' = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.") s