X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=32279fdea471a0c055a50ccb39cd6bd8491fd9de;hb=e273d2759db01787f0599a1cbe9059864e1704d7;hp=ad4736471bbf8798d06c6c49c21509fb9d5e4442;hpb=322d29e9564826fc9e7e3c743c38a0d5d353594e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index ad47364..32279fd 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -59,9 +59,13 @@ createEntity hsfunc fdata =
       in
         setEntity hsfunc entity'
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> Maybe (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      (mkVHDLId nm, vhdl_ty ty)
+      if isPortSigUse $ sigUse info
+        then
+          Just (mkVHDLId nm, vhdl_ty ty)
+        else
+          Nothing
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
@@ -87,7 +91,7 @@ createEntityAST hsfunc args res =
             ++ clk_port
     mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] 
     mapToPorts mode m =
-      map (mkIfaceSigDec mode) (Foldable.toList m)
+      Maybe.catMaybes $ map (mkIfaceSigDec mode) (Foldable.toList m)
     -- Add a clk port if we have state
     clk_port = if hasState hsfunc
       then
@@ -98,10 +102,11 @@ createEntityAST hsfunc args res =
 -- | Create a port declaration
 mkIfaceSigDec ::
   AST.Mode                         -- | The mode for the port (In / Out)
-  -> (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
-  -> AST.IfaceSigDec               -- | The resulting port declaration
+  -> Maybe (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
+  -> Maybe AST.IfaceSigDec               -- | The resulting port declaration
 
-mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
+mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
+mkIfaceSigDec _ Nothing = Nothing
 
 -- | Generate a VHDL entity name for the given hsfunc
 mkEntityId hsfunc =
@@ -130,7 +135,7 @@ createArchitecture hsfunc fdata =
                       (getEntityId fdata)
       -- Create signal declarations for all signals that are not in args and
       -- res
-      let sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ]
+      let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
       -- Create component instantiations for all function applications
       insts <- mapM (mkCompInsSm sigs) apps
       let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
@@ -151,9 +156,13 @@ mkStateProcSm (num, old, new) =
     rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
     statement   = AST.IfSm rising_edge_clk [assign] [] Nothing
 
-mkSigDec :: SignalInfo -> AST.SigDec
+mkSigDec :: SignalInfo -> Maybe AST.SigDec
 mkSigDec info =
-    AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+  let use = sigUse info in
+  if isInternalSigUse use || isStateSigUse use then
+    Just $ AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+  else
+    Nothing
   where
     ty = sigTy info
 
@@ -167,8 +176,8 @@ getSignalId info =
 
 -- | Transforms a flat function application to a VHDL component instantiation.
 mkCompInsSm ::
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
+  [(SignalId, SignalInfo)] -- | The signals in the current architecture
+  -> FApp                       -- | The application to look at.
   -> VHDLState AST.CompInsSm    -- | The corresponding VHDL component instantiation.
 
 mkCompInsSm sigs app = do
@@ -186,14 +195,14 @@ mkCompInsSm sigs app = do
   return $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
 
 mkAssocElems :: 
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
+  [(SignalId, SignalInfo)] -- | The signals in the current architecture
+  -> FApp                       -- | The application to look at.
   -> Entity                     -- | The entity to map against.
   -> [AST.AssocElem]            -- | The resulting port maps
 
 mkAssocElems sigmap app entity =
     -- Create the actual AssocElems
-    zipWith mkAssocElem ports sigs
+    Maybe.catMaybes $ zipWith mkAssocElem ports sigs
   where
     -- Turn the ports and signals from a map into a flat list. This works,
     -- since the maps must have an identical form by definition. TODO: Check
@@ -203,12 +212,12 @@ mkAssocElems sigmap app entity =
     arg_sigs  = (concat (map Foldable.toList (appArgs app)))
     res_sigs  = Foldable.toList (appRes app)
     -- Extract the id part from the (id, type) tuple
-    ports     = (map fst (arg_ports ++ res_ports)) 
+    ports     = (map (fmap fst) (arg_ports ++ res_ports)) 
     -- Translate signal numbers into names
     sigs      = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs))
 
 -- | Look up a signal in the signal name map
-lookupSigName :: [(UnnamedSignal, SignalInfo)] -> UnnamedSignal -> String
+lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
 lookupSigName sigs sig = name
   where
     info = Maybe.fromMaybe
@@ -219,8 +228,9 @@ lookupSigName sigs sig = name
       (sigName info)
 
 -- | Create an VHDL port -> signal association
-mkAssocElem :: AST.VHDLId -> String -> AST.AssocElem
-mkAssocElem port signal = Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) 
+mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
+mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) 
+mkAssocElem Nothing _ = Nothing
 
 -- | Extracts the generated entity id from the given funcdata
 getEntityId :: FuncData -> Maybe AST.VHDLId