X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=2c20663b0bf9d481f4d437c2be482c3e112e001a;hb=dc283627ed31bc4ea22ae99669ce6bdf3fb95ac5;hp=eb454203ebeda699ebcc9c595f4a6f395dbdfee7;hpb=3f4773d25a4c44a0e4c9503806562a6741da3508;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index eb45420..2c20663 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -264,6 +264,11 @@ mkConcSm ::
   (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
   -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
 
+
+-- Ignore Cast expressions, they should not longer have any meaning as long as
+-- the type works out.
+mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr)
+
 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
   let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
   let valargs' = filter isValArg args
@@ -293,9 +298,8 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
         Just (arg_count, builder) ->
           if length valargs == arg_count then
             let
-              sigs = map (bndrToString.varBndr) valargs
-              sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
-              func = builder sigsNames
+              sigs = map (varToVHDLExpr.varBndr) valargs
+              func = builder sigs
               src_wform = AST.Wform [AST.WformElem func Nothing]
               dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
               assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)