X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=2c20663b0bf9d481f4d437c2be482c3e112e001a;hb=dc283627ed31bc4ea22ae99669ce6bdf3fb95ac5;hp=b2d5b30e448964d450934b88a343d309a44c8b09;hpb=c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index b2d5b30..2c20663 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -298,9 +298,8 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
         Just (arg_count, builder) ->
           if length valargs == arg_count then
             let
-              sigs = map (bndrToString.varBndr) valargs
-              sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
-              func = builder sigsNames
+              sigs = map (varToVHDLExpr.varBndr) valargs
+              func = builder sigs
               src_wform = AST.Wform [AST.WformElem func Nothing]
               dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
               assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)