X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=1c7eba9ea2e848fbca70c620357e1b0e9fb09f85;hb=9b7d00ad53acfc821840051ef693d87470b4462b;hp=ee61c500a6916f676fd75e1c7566d6d8bb868eab;hpb=157dae90bdd7c45613c6ad6185383a1137b2323f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index ee61c50..1c7eba9 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -8,6 +8,7 @@ import qualified Maybe
 import qualified Control.Monad as Monad
 
 import qualified Type
+import qualified TysWiredIn
 import qualified Name
 import qualified TyCon
 import Outputable ( showSDoc, ppr )
@@ -20,6 +21,19 @@ import FlattenTypes
 import TranslatorTypes
 import Pretty
 
+getDesignFile :: VHDLState AST.DesignFile
+getDesignFile = do
+  -- Extract the library units generated from all the functions in the
+  -- session.
+  funcs <- getFuncs
+  let units = concat $ map getLibraryUnits funcs
+  let context = [
+        AST.Library $ mkVHDLId "IEEE",
+        AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
+  return $ AST.DesignFile 
+    context
+    units
+  
 -- | Create an entity for a given function
 createEntity ::
   HsFunction        -- | The function signature
@@ -46,9 +60,13 @@ createEntity hsfunc fdata =
       in
         setEntity hsfunc entity'
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> Maybe (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      (mkVHDLId nm, vhdl_ty ty)
+      if isPortSigUse $ sigUse info
+        then
+          Just (mkVHDLId nm, vhdl_ty ty)
+        else
+          Nothing
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
@@ -74,7 +92,7 @@ createEntityAST hsfunc args res =
             ++ clk_port
     mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] 
     mapToPorts mode m =
-      map (mkIfaceSigDec mode) (Foldable.toList m)
+      Maybe.catMaybes $ map (mkIfaceSigDec mode) (Foldable.toList m)
     -- Add a clk port if we have state
     clk_port = if hasState hsfunc
       then
@@ -85,10 +103,11 @@ createEntityAST hsfunc args res =
 -- | Create a port declaration
 mkIfaceSigDec ::
   AST.Mode                         -- | The mode for the port (In / Out)
-  -> (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
-  -> AST.IfaceSigDec               -- | The resulting port declaration
+  -> Maybe (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
+  -> Maybe AST.IfaceSigDec               -- | The resulting port declaration
 
-mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
+mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
+mkIfaceSigDec _ Nothing = Nothing
 
 -- | Generate a VHDL entity name for the given hsfunc
 mkEntityId hsfunc =
@@ -111,22 +130,21 @@ createArchitecture hsfunc fdata =
       let sigs = flat_sigs flatfunc
       let args = flat_args flatfunc
       let res  = flat_res  flatfunc
-      let apps = flat_apps flatfunc
+      let defs = flat_defs flatfunc
       let entity_id = Maybe.fromMaybe
                       (error $ "Building architecture without an entity? This should not happen!")
                       (getEntityId fdata)
       -- Create signal declarations for all signals that are not in args and
       -- res
-      let sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ]
-      -- Create component instantiations for all function applications
-      insts <- mapM (mkCompInsSm sigs) apps
+      let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
+      -- Create concurrent statements for all signal definitions
+      statements <- mapM (mkConcSm sigs) defs
       let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
-      let insts' = map AST.CSISm insts
       let procs' = map AST.CSPSm procs
-      let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (insts' ++ procs')
+      let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
       setArchitecture hsfunc arch
 
-mkStateProcSm :: (Int, SignalInfo, SignalInfo) -> AST.ProcSm
+mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
 mkStateProcSm (num, old, new) =
   AST.ProcSm label [clk] [statement]
   where
@@ -138,9 +156,13 @@ mkStateProcSm (num, old, new) =
     rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
     statement   = AST.IfSm rising_edge_clk [assign] [] Nothing
 
-mkSigDec :: SignalInfo -> AST.SigDec
+mkSigDec :: SignalInfo -> Maybe AST.SigDec
 mkSigDec info =
-    AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+  let use = sigUse info in
+  if isInternalSigUse use || isStateSigUse use then
+    Just $ AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+  else
+    Nothing
   where
     ty = sigTy info
 
@@ -152,14 +174,13 @@ getSignalId info =
       (error $ "Unnamed signal? This should not happen!")
       (sigName info)
 
--- | Transforms a flat function application to a VHDL component instantiation.
-mkCompInsSm ::
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
-  -> VHDLState AST.CompInsSm    -- | The corresponding VHDL component instantiation.
+-- | Transforms a signal definition into a VHDL concurrent statement
+mkConcSm ::
+  [(SignalId, SignalInfo)] -- | The signals in the current architecture
+  -> SigDef                -- | The signal definition
+  -> VHDLState AST.ConcSm    -- | The corresponding VHDL component instantiation.
 
-mkCompInsSm sigs app = do
-  let hsfunc = appFunc app
+mkConcSm sigs (FApp hsfunc args res) = do
   fdata_maybe <- getFunc hsfunc
   let fdata = Maybe.fromMaybe
         (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' that is not in the session? This should not happen!")
@@ -169,33 +190,68 @@ mkCompInsSm sigs app = do
         (funcEntity fdata)
   let entity_id = ent_id entity
   label <- uniqueName (AST.fromVHDLId entity_id)
-  let portmaps = mkAssocElems sigs app entity
-  return $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+  let portmaps = mkAssocElems sigs args res entity
+  return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+
+mkConcSm sigs (UncondDef src dst) = do
+  let src_expr  = vhdl_expr src
+  let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
+  let dst_name  = AST.NSimple (getSignalId $ signalInfo sigs dst)
+  let assign    = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
+  return $ AST.CSSASm assign
+  where
+    vhdl_expr (Left id) = mkIdExpr sigs id
+    vhdl_expr (Right expr) =
+      case expr of
+        (EqLit id lit) ->
+          (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
+        (Literal lit) ->
+          AST.PrimLit lit
+        (Eq a b) ->
+          (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
+
+mkConcSm sigs (CondDef cond true false dst) = do
+  let cond_expr  = mkIdExpr sigs cond
+  let true_expr  = mkIdExpr sigs true
+  let false_expr  = mkIdExpr sigs false
+  let false_wform = AST.Wform [AST.WformElem false_expr Nothing]
+  let true_wform = AST.Wform [AST.WformElem true_expr Nothing]
+  let whenelse = AST.WhenElse true_wform cond_expr
+  let dst_name  = AST.NSimple (getSignalId $ signalInfo sigs dst)
+  let assign    = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
+  return $ AST.CSSASm assign
+
+-- | Turn a SignalId into a VHDL Expr
+mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
+mkIdExpr sigs id =
+  let src_name  = AST.NSimple (getSignalId $ signalInfo sigs id) in
+  AST.PrimName src_name
 
 mkAssocElems :: 
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
+  [(SignalId, SignalInfo)]      -- | The signals in the current architecture
+  -> [SignalMap]                -- | The signals that are applied to function
+  -> SignalMap                  -- | the signals in which to store the function result
   -> Entity                     -- | The entity to map against.
   -> [AST.AssocElem]            -- | The resulting port maps
 
-mkAssocElems sigmap app entity =
+mkAssocElems sigmap args res entity =
     -- Create the actual AssocElems
-    zipWith mkAssocElem ports sigs
+    Maybe.catMaybes $ zipWith mkAssocElem ports sigs
   where
     -- Turn the ports and signals from a map into a flat list. This works,
     -- since the maps must have an identical form by definition. TODO: Check
     -- the similar form?
     arg_ports = concat (map Foldable.toList (ent_args entity))
     res_ports = Foldable.toList (ent_res entity)
-    arg_sigs  = (concat (map Foldable.toList (appArgs app)))
-    res_sigs  = Foldable.toList (appRes app)
+    arg_sigs  = (concat (map Foldable.toList args))
+    res_sigs  = Foldable.toList res
     -- Extract the id part from the (id, type) tuple
-    ports     = (map fst (arg_ports ++ res_ports)) 
+    ports     = (map (fmap fst) (arg_ports ++ res_ports)) 
     -- Translate signal numbers into names
     sigs      = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs))
 
 -- | Look up a signal in the signal name map
-lookupSigName :: [(UnnamedSignal, SignalInfo)] -> UnnamedSignal -> String
+lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
 lookupSigName sigs sig = name
   where
     info = Maybe.fromMaybe
@@ -206,8 +262,9 @@ lookupSigName sigs sig = name
       (sigName info)
 
 -- | Create an VHDL port -> signal association
-mkAssocElem :: AST.VHDLId -> String -> AST.AssocElem
-mkAssocElem port signal = Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) 
+mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
+mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal))) 
+mkAssocElem Nothing _ = Nothing
 
 -- | Extracts the generated entity id from the given funcdata
 getEntityId :: FuncData -> Maybe AST.VHDLId
@@ -237,6 +294,10 @@ getLibraryUnits (hsfunc, fdata) =
 bit_ty :: AST.TypeMark
 bit_ty = AST.unsafeVHDLBasicId "Bit"
 
+-- | The VHDL Boolean type
+bool_ty :: AST.TypeMark
+bool_ty = AST.unsafeVHDLBasicId "Boolean"
+
 -- | The VHDL std_logic
 std_logic_ty :: AST.TypeMark
 std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
@@ -250,14 +311,18 @@ vhdl_ty ty = Maybe.fromMaybe
 -- Translate a Haskell type to a VHDL type
 vhdl_ty_maybe :: Type.Type -> Maybe AST.TypeMark
 vhdl_ty_maybe ty =
-  case Type.splitTyConApp_maybe ty of
-    Just (tycon, args) ->
-      let name = TyCon.tyConName tycon in
-        -- TODO: Do something more robust than string matching
-        case Name.getOccString name of
-          "Bit"      -> Just bit_ty
-          otherwise  -> Nothing
-    otherwise -> Nothing
+  if Type.coreEqType ty TysWiredIn.boolTy
+    then
+      Just bool_ty
+    else
+      case Type.splitTyConApp_maybe ty of
+        Just (tycon, args) ->
+          let name = TyCon.tyConName tycon in
+            -- TODO: Do something more robust than string matching
+            case Name.getOccString name of
+              "Bit"      -> Just std_logic_ty
+              otherwise  -> Nothing
+        otherwise -> Nothing
 
 -- Shortcut
 mkVHDLId :: String -> AST.VHDLId