X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDL.hs;h=1c7eba9ea2e848fbca70c620357e1b0e9fb09f85;hb=9b7d00ad53acfc821840051ef693d87470b4462b;hp=57bebfc12ab0265369ecb7028a6a8740c579d2d6;hpb=1e30fe04f4c285970ad2d5e23930dd935b4214fa;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 57bebfc..1c7eba9 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -205,6 +205,10 @@ mkConcSm sigs (UncondDef src dst) = do
       case expr of
         (EqLit id lit) ->
           (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
+        (Literal lit) ->
+          AST.PrimLit lit
+        (Eq a b) ->
+          (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
 
 mkConcSm sigs (CondDef cond true false dst) = do
   let cond_expr  = mkIdExpr sigs cond
@@ -316,7 +320,7 @@ vhdl_ty_maybe ty =
           let name = TyCon.tyConName tycon in
             -- TODO: Do something more robust than string matching
             case Name.getOccString name of
-              "Bit"      -> Just bit_ty
+              "Bit"      -> Just std_logic_ty
               otherwise  -> Nothing
         otherwise -> Nothing