X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=eb4e59f5da01448e8390445e6a511593c626941d;hb=6917dbf733c6c9d7ecfe1796133664be26b6b1dc;hp=841f63b892c2f330adfa88bca5c837cf5a7ada23;hpb=6a57a063a1765dea8e72628d59efaaa5ecfa66e1;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 841f63b..eb4e59f 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -14,6 +14,7 @@ import qualified Control.Monad.State as State
 import qualified Data.Foldable as Foldable
 import Name
 import qualified Data.Map as Map
+import Data.Accessor
 import Data.Generics
 import NameEnv ( lookupNameEnv )
 import qualified HscTypes
@@ -91,10 +92,12 @@ moduleToVHDL core list = do
       mapM addBuiltIn builtin_funcs
       -- Create entities and architectures for them
       Monad.zipWithM processBind statefuls binds
-      modFuncs nameFlatFunction
-      modFuncs VHDL.createEntity
-      modFuncs VHDL.createArchitecture
-      VHDL.getDesignFiles
+      modFuncMap $ Map.map (fdFlatFunc ^: (fmap nameFlatFunction))
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdEntity ^= (VHDL.createEntity hsfunc fdata) $ fdata)
+      funcs <- getFuncMap
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdArch ^= (VHDL.createArchitecture funcs hsfunc fdata) $ fdata)
+      funcs <- getFuncs
+      return $ VHDL.getDesignFiles (map snd funcs)
 
 -- | Write the given design file to a file inside the given dir
 --   The first library unit in the designfile must be an entity, whose name
@@ -331,21 +334,15 @@ mkHsFunction f ty stateful=
 
 -- | Adds signal names to the given FlatFunction
 nameFlatFunction ::
-  HsFunction
-  -> FuncData
-  -> VHDLState ()
+  FlatFunction
+  -> FlatFunction
 
-nameFlatFunction hsfunc fdata =
-  let func = flatFunc fdata in
-  case func of
-    -- Skip (builtin) functions without a FlatFunction
-    Nothing -> do return ()
-    -- Name the signals in all other functions
-    Just flatfunc ->
-      let s = flat_sigs flatfunc in
-      let s' = map nameSignal s in
-      let flatfunc' = flatfunc { flat_sigs = s' } in
-      setFlatFunc hsfunc flatfunc'
+nameFlatFunction flatfunc =
+  -- Name the signals
+  let 
+    s = flat_sigs flatfunc
+    s' = map nameSignal s in
+  flatfunc { flat_sigs = s' }
   where
     nameSignal :: (SignalId, SignalInfo) -> (SignalId, SignalInfo)
     nameSignal (id, info) =
@@ -387,7 +384,7 @@ addBuiltIn (BuiltIn name args res) = do
     setEntity hsfunc entity
   where
     hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
-    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing
 
 builtin_funcs = 
   [