X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=9ce7206c9df9bd841bd0c5a4e7cccabe1d392b3f;hb=678eabd616fa5f40882f752a3ca49633b5fe64a9;hp=d0738d3f9175a8058d3621bdf17479d52ff3b517;hpb=535eeae192a34920407f47626fea2534bb5c263b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index d0738d3..9ce7206 100644 --- a/Translator.hs +++ b/Translator.hs @@ -37,6 +37,7 @@ import HsValueMap import Pretty import Flatten import FlattenTypes +import VHDLTypes import qualified VHDL main = @@ -68,9 +69,16 @@ main = mapM addBuiltIn builtin_funcs -- Create entities and architectures for them mapM processBind binds + modFuncs nameFlatFunction + modFuncs VHDL.createEntity + modFuncs VHDL.createArchitecture + -- Extract the library units generated from all the functions in the + -- session. + funcs <- getFuncs + let units = concat $ map VHDL.getLibraryUnits funcs return $ AST.DesignFile [] - [] + units findBind :: [CoreBind] -> String -> Maybe CoreBind findBind binds lookfor = @@ -109,7 +117,7 @@ flattenBind hsfunc bind@(NonRec var expr) = do let flatfunc = flattenFunction hsfunc bind addFunc hsfunc setFlatFunc hsfunc flatfunc - let used_hsfuncs = map appFunc (apps flatfunc) + let used_hsfuncs = map appFunc (flat_apps flatfunc) State.mapM resolvFunc used_hsfuncs return () @@ -166,6 +174,24 @@ mkHsFunction f ty = error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty) otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports." +-- | Adds signal names to the given FlatFunction +nameFlatFunction :: + HsFunction + -> FuncData + -> VHDLState () + +nameFlatFunction hsfunc fdata = + let func = flatFunc fdata in + case func of + -- Skip (builtin) functions without a FlatFunction + Nothing -> do return () + -- Name the signals in all other functions + Just flatfunc -> + let s = flat_sigs flatfunc in + let s' = map (\(id, (SignalInfo Nothing use ty)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)) use ty)) s in + let flatfunc' = flatfunc { flat_sigs = s' } in + setFlatFunc hsfunc flatfunc' + -- | Splits a tuple type into a list of element types, or Nothing if the type -- is not a tuple type. splitTupleType :: @@ -186,13 +212,20 @@ type PortMap = HsValueMap (String, AST.TypeMark) -- | A consise representation of a builtin function data BuiltIn = BuiltIn String [PortMap] PortMap +-- | Map a port specification of a builtin function to a VHDL Signal to put in +-- a VHDLSignalMap +toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap +toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty)) + -- | Translate a concise representation of a builtin function to something -- that can be put into FuncMap directly. addBuiltIn :: BuiltIn -> VHDLState () addBuiltIn (BuiltIn name args res) = do addFunc hsfunc + setEntity hsfunc entity where hsfunc = HsFunction name (map useAsPort args) (useAsPort res) + entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing builtin_funcs = [