X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=98380606884c24ba953a07216d1bb788d1747d22;hb=1e30fe04f4c285970ad2d5e23930dd935b4214fa;hp=53befc228e6ef947107b72141d9cb7c713fd5606;hpb=c77b7153a516c7dab7824520dd391189270a570b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 53befc2..9838060 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -43,9 +43,9 @@ import qualified VHDL
 
 main = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule "Alu.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core ["salu"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"