X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=77394e41c65697d473f501857a26caabc29e03a7;hb=8bc898050866c1684bd02b3d5437c12847106b8f;hp=8f1c3fd4d6e1a49326c2086cca2b756b8fc798ac;hpb=b2e147bebb4ac8195971cd427903e53082f3bdf6;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index 8f1c3fd..77394e4 100644 --- a/Translator.hs +++ b/Translator.hs @@ -45,28 +45,24 @@ main = --core <- GHC.compileToCoreSimplified "Adders.hs" core <- GHC.compileToCoreSimplified "Adders.hs" --liftIO $ printBinds (cm_binds core) - let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["full_adder", "half_adder"] + let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"] liftIO $ printBinds binds -- Turn bind into VHDL - let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 []) + let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession 0 []) liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl" + liftIO $ putStr $ "\n\nFinal session:\n" ++ show sess return () where -- Turns the given bind into VHDL mkVHDL binds = do -- Add the builtin functions mapM (uncurry addFunc) builtin_funcs - -- Get the function signatures - funcs <- mapM mkHWFunction binds - -- Add them to the session - mapM (uncurry addFunc) funcs - let entities = map getEntity (snd $ unzip funcs) - -- Create architectures for them - archs <- mapM getArchitecture binds + -- Create entities and architectures for them + units <- mapM expandBind binds return $ AST.DesignFile [] - ((map AST.LUEntity entities) ++ (map AST.LUArch archs)) + (concat units) printTarget (Target (TargetFile file (Just x)) obj Nothing) = print $ show file @@ -128,7 +124,8 @@ expandExpr binds lam@(Lam b expr) = do -- Find the type of the binder let (arg_ty, _) = Type.splitFunTy (CoreUtils.exprType lam) -- Create signal names for the binder - let arg_signal = getPortNameMapForTy ("xxx") arg_ty + -- TODO: We assume arguments are ports here + let arg_signal = getPortNameMapForTy ("xxx") arg_ty (useAsPort arg_ty) -- Create the corresponding signal declarations let signal_decls = mkSignalsFromMap arg_signal -- Add the binder to the list of binds @@ -142,10 +139,10 @@ expandExpr binds lam@(Lam b expr) = do res_signal') expandExpr binds (Var id) = - return ([], [], [], Single (signal_id, ty)) + return ([], [], [], bind) where -- Lookup the id in our binds map - Single (signal_id, ty) = Maybe.fromMaybe + bind = Maybe.fromMaybe (error $ "Argument " ++ getOccString id ++ "is unknown") (lookup id binds) @@ -254,13 +251,14 @@ expandApplicationExpr binds ty f args = do -- Generate a unique name for the application appname <- uniqueName ("app_" ++ name) -- Lookup the hwfunction to instantiate - HWFunction vhdl_id inports outport <- getHWFunc name + HWFunction vhdl_id inports outport <- getHWFunc (appToHsFunction f args ty) -- Expand each of the args, so each of them is reduced to output signals (arg_signal_decls, arg_statements, arg_res_signals) <- expandArgs binds args -- Bind each of the input ports to the expanded arguments let inmaps = concat $ zipWith createAssocElems inports arg_res_signals -- Create signal names for our result - let res_signal = getPortNameMapForTy (appname ++ "_out") ty + -- TODO: We assume the result is a port here + let res_signal = getPortNameMapForTy (appname ++ "_out") ty (useAsPort ty) -- Create the corresponding signal declarations let signal_decls = mkSignalsFromMap res_signal -- Bind each of the output ports to our output signals @@ -357,16 +355,34 @@ mapOutputPorts (Single (portname, _)) (Single (signalname, _)) = mapOutputPorts (Tuple ports) (Tuple signals) = concat (zipWith mapOutputPorts ports signals) +expandBind :: + CoreBind -- The binder to expand into VHDL + -> VHDLState [AST.LibraryUnit] -- The resulting VHDL + +expandBind (Rec _) = error "Recursive binders not supported" + +expandBind bind@(NonRec var expr) = do + -- Create the function signature + let ty = CoreUtils.exprType expr + let hsfunc = mkHsFunction var ty + hwfunc <- mkHWFunction bind hsfunc + -- Add it to the session + addFunc hsfunc hwfunc + arch <- getArchitecture hwfunc expr + let entity = getEntity hwfunc + return $ [ + AST.LUEntity entity, + AST.LUArch arch ] + getArchitecture :: - CoreBind -- The binder to expand into an architecture + HWFunction -- The function to generate an architecture for + -> CoreExpr -- The expression that is bound to the function -> VHDLState AST.ArchBody -- The resulting architecture -getArchitecture (Rec _) = error "Recursive binders not supported" - -getArchitecture (NonRec var expr) = do - let name = (getOccString var) - HWFunction vhdl_id inports outport <- getHWFunc name - sess <- State.get +getArchitecture hwfunc expr = do + -- Unpack our hwfunc + let HWFunction vhdl_id inports outport = hwfunc + -- Expand the expression into an architecture body (signal_decls, statements, arg_signals, res_signal) <- expandExpr [] expr let inport_assigns = concat $ zipWith createSignalAssignments arg_signals inports let outport_assigns = createSignalAssignments outport res_signal @@ -396,6 +412,10 @@ mkIfaceSigDecs mode (Single (port_id, ty)) = mkIfaceSigDecs mode (Tuple ports) = concat $ map (mkIfaceSigDecs mode) ports +-- Unused values (state) don't generate ports +mkIfaceSigDecs mode Unused = + [] + -- Create concurrent assignments of one map of signals to another. The maps -- should have a similar form. createSignalAssignments :: @@ -417,8 +437,16 @@ createSignalAssignments (Single (dst, _)) (Single (src, _)) = createSignalAssignments (Tuple dsts) (Tuple srcs) = concat $ zipWith createSignalAssignments dsts srcs +createSignalAssignments Unused (Single (src, _)) = + -- Write state + [] + +createSignalAssignments (Single (src, _)) Unused = + -- Read state + [] + createSignalAssignments dst src = - error $ "Non matching source and destination: " ++ show dst ++ "\nand\n" ++ show src + error $ "Non matching source and destination: " ++ show dst ++ " <= " ++ show src type SignalNameMap = HsValueMap (AST.VHDLId, AST.TypeMark) @@ -428,20 +456,48 @@ type SignalNameMap = HsValueMap (AST.VHDLId, AST.TypeMark) data HsValueMap mapto = Tuple [HsValueMap mapto] | Single mapto - deriving (Show) + | Unused + deriving (Show, Eq) + +-- | Creates a HsValueMap with the same structure as the given type, using the +-- given function for mapping the single types. +mkHsValueMap :: + (Type -> HsValueMap mapto) -- ^ A function to map single value Types + -- (basically anything but tuples) to a + -- HsValueMap (not limited to the Single + -- constructor) + -> Type -- ^ The type to map to a HsValueMap + -> HsValueMap mapto -- ^ The resulting map + +mkHsValueMap f ty = + case Type.splitTyConApp_maybe ty of + Just (tycon, args) -> + if (TyCon.isTupleTyCon tycon) + then + -- Handle tuple construction especially + Tuple (map (mkHsValueMap f) args) + else + -- And let f handle the rest + f ty + -- And let f handle the rest + Nothing -> f ty -- Generate a port name map (or multiple for tuple types) in the given direction for -- each type given. -getPortNameMapForTys :: String -> Int -> [Type] -> [SignalNameMap] -getPortNameMapForTys prefix num [] = [] -getPortNameMapForTys prefix num (t:ts) = - (getPortNameMapForTy (prefix ++ show num) t) : getPortNameMapForTys prefix (num + 1) ts +getPortNameMapForTys :: String -> Int -> [Type] -> [HsUseMap] -> [SignalNameMap] +getPortNameMapForTys prefix num [] [] = [] +getPortNameMapForTys prefix num (t:ts) (u:us) = + (getPortNameMapForTy (prefix ++ show num) t u) : getPortNameMapForTys prefix (num + 1) ts us + +getPortNameMapForTy :: String -> Type -> HsUseMap -> SignalNameMap +getPortNameMapForTy name _ (Single State) = + Unused -getPortNameMapForTy :: String -> Type -> SignalNameMap -getPortNameMapForTy name ty = +getPortNameMapForTy name ty use = if (TyCon.isTupleTyCon tycon) then + let (Tuple uses) = use in -- Expand tuples we find - Tuple (getPortNameMapForTys name 0 args) + Tuple (getPortNameMapForTys name 0 args uses) else -- Assume it's a type constructor application, ie simple data type Single ((AST.unsafeVHDLBasicId name), (vhdl_ty ty)) where @@ -458,46 +514,124 @@ data HWFunction = HWFunction { -- A function that is available in hardware -- output ports. mkHWFunction :: CoreBind -- The core binder to generate the interface for - -> VHDLState (String, HWFunction) -- The name of the function and its interface + -> HsFunction -- The HsFunction describing the function + -> VHDLState HWFunction -- The function interface -mkHWFunction (NonRec var expr) = - return (name, HWFunction (mkVHDLId name) inports outport) +mkHWFunction (NonRec var expr) hsfunc = + return $ HWFunction (mkVHDLId name) inports outport where name = getOccString var ty = CoreUtils.exprType expr - (fargs, res) = Type.splitFunTys ty - args = if length fargs == 1 then fargs else (init fargs) - --state = if length fargs == 1 then () else (last fargs) + (args, res) = Type.splitFunTys ty inports = case args of -- Handle a single port specially, to prevent an extra 0 in the name - [port] -> [getPortNameMapForTy "portin" port] - ps -> getPortNameMapForTys "portin" 0 ps - outport = getPortNameMapForTy "portout" res + [port] -> [getPortNameMapForTy "portin" port (head $ hsArgs hsfunc)] + ps -> getPortNameMapForTys "portin" 0 ps (hsArgs hsfunc) + outport = getPortNameMapForTy "portout" res (hsRes hsfunc) -mkHWFunction (Rec _) = +mkHWFunction (Rec _) _ = error "Recursive binders not supported" +-- | How is a given (single) value in a function's type (ie, argument or +-- return value) used? +data HsValueUse = + Port -- ^ Use it as a port (input or output) + | State --- ^ Use it as state (input or output) + deriving (Show, Eq) + +useAsPort = mkHsValueMap (\x -> Single Port) +useAsState = mkHsValueMap (\x -> Single State) + +type HsUseMap = HsValueMap HsValueUse + +-- | This type describes a particular use of a Haskell function and is used to +-- look up an appropriate hardware description. +data HsFunction = HsFunction { + hsName :: String, -- ^ What was the name of the original Haskell function? + hsArgs :: [HsUseMap], -- ^ How are the arguments used? + hsRes :: HsUseMap -- ^ How is the result value used? +} deriving (Show, Eq) + +-- | Translate a function application to a HsFunction. i.e., which function +-- do you need to translate this function application. +appToHsFunction :: + Var.Var -- ^ The function to call + -> [CoreExpr] -- ^ The function arguments + -> Type -- ^ The return type + -> HsFunction -- ^ The needed HsFunction + +appToHsFunction f args ty = + HsFunction hsname hsargs hsres + where + mkPort = \x -> Single Port + hsargs = map (mkHsValueMap mkPort . CoreUtils.exprType) args + hsres = mkHsValueMap mkPort ty + hsname = getOccString f + +-- | Translate a top level function declaration to a HsFunction. i.e., which +-- interface will be provided by this function. This function essentially +-- defines the "calling convention" for hardware models. +mkHsFunction :: + Var.Var -- ^ The function defined + -> Type -- ^ The function type (including arguments!) + -> HsFunction -- ^ The resulting HsFunction + +mkHsFunction f ty = + HsFunction hsname hsargs hsres + where + hsname = getOccString f + (arg_tys, res_ty) = Type.splitFunTys ty + -- The last argument must be state + state_ty = last arg_tys + state = useAsState state_ty + -- All but the last argument are inports + inports = map useAsPort (init arg_tys) + hsargs = inports ++ [state] + hsres = case splitTupleType res_ty of + -- Result type must be a two tuple (state, ports) + Just [outstate_ty, outport_ty] -> if Type.coreEqType state_ty outstate_ty + then + Tuple [state, useAsPort outport_ty] + else + error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty) + otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports." + data VHDLSession = VHDLSession { - nameCount :: Int, -- A counter that can be used to generate unique names - funcs :: [(String, HWFunction)] -- All functions available, indexed by name + nameCount :: Int, -- A counter that can be used to generate unique names + funcs :: [(HsFunction, HWFunction)] -- All functions available } deriving (Show) type VHDLState = State.State VHDLSession -- Add the function to the session -addFunc :: String -> HWFunction -> VHDLState () -addFunc name f = do +addFunc :: HsFunction -> HWFunction -> VHDLState () +addFunc hsfunc hwfunc = do fs <- State.gets funcs -- Get the funcs element from the session - State.modify (\x -> x {funcs = (name, f) : fs }) -- Prepend name and f + State.modify (\x -> x {funcs = (hsfunc, hwfunc) : fs }) -- Prepend name and f -- Lookup the function with the given name in the current session. Errors if -- it was not found. -getHWFunc :: String -> VHDLState HWFunction -getHWFunc name = do +getHWFunc :: HsFunction -> VHDLState HWFunction +getHWFunc hsfunc = do fs <- State.gets funcs -- Get the funcs element from the session return $ Maybe.fromMaybe - (error $ "Function " ++ name ++ "is unknown? This should not happen!") - (lookup name fs) + (error $ "Function " ++ (hsName hsfunc) ++ "is unknown? This should not happen!") + (lookup hsfunc fs) + +-- | Splits a tuple type into a list of element types, or Nothing if the type +-- is not a tuple type. +splitTupleType :: + Type -- ^ The type to split + -> Maybe [Type] -- ^ The tuples element types + +splitTupleType ty = + case Type.splitTyConApp_maybe ty of + Just (tycon, args) -> if TyCon.isTupleTyCon tycon + then + Just args + else + Nothing + Nothing -> Nothing -- Makes the given name unique by appending a unique number. -- This does not do any checking against existing names, so it only guarantees @@ -514,10 +648,10 @@ mkVHDLId = AST.unsafeVHDLBasicId builtin_funcs = [ - ("hwxor", HWFunction (mkVHDLId "hwxor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), - ("hwand", HWFunction (mkVHDLId "hwand") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), - ("hwor", HWFunction (mkVHDLId "hwor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), - ("hwnot", HWFunction (mkVHDLId "hwnot") [Single (mkVHDLId "i", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))) + (HsFunction "hwxor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwxor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), + (HsFunction "hwand" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwand") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), + (HsFunction "hwor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))), + (HsFunction "hwnot" [(Single Port)] (Single Port), HWFunction (mkVHDLId "hwnot") [Single (mkVHDLId "i", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))) ] vhdl_bit_ty :: AST.TypeMark