X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=75a875bf8426e43f157e0ab6bf07f3435329326d;hb=e771c40c12c3d93a1c59b396cf862cb0ac617d94;hp=c16406be3aef2781484251c56a21d3e5fb394f54;hpb=5b7046a2981a1e65483527cab15314dd140e0002;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index c16406b..75a875b 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,10 +42,14 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "salu"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["dff"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
@@ -56,6 +60,7 @@ listBind filename name = do
   let binds = findBinds core [name]
   putStr "\n"
   putStr $ prettyShow binds
+  putStr $ showSDoc $ ppr binds
   putStr "\n\n"
 
 -- | Translate the binds with the given names from the given core module to