X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=6c9f40e8c9772212876c2e6a09c2019f6a726cbc;hb=71b626267baa4812f79944bfc1af93dfe0e850ed;hp=2de4803139237f08810d6bdfb0f75320787cb88f;hpb=3b7b9be750c73e0545d27cfdc95fc73ade1c8459;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index 2de4803..6c9f40e 100644 --- a/Translator.hs +++ b/Translator.hs @@ -18,6 +18,9 @@ import Outputable ( showSDoc, ppr ) import GHC.Paths ( libdir ) import DynFlags ( defaultDynFlags ) import List ( find ) +import qualified List +import qualified Monad + -- The following modules come from the ForSyDe project. They are really -- internal modules, so ForSyDe.cabal has to be modified prior to installing -- ForSyDe to get access to these modules. @@ -40,24 +43,24 @@ main = --load LoadAllTargets --core <- GHC.compileToCoreSimplified "Adders.hs" core <- GHC.compileToCoreSimplified "Adders.hs" - liftIO $ printBinds (cm_binds core) - let bind = findBind "invinv" (cm_binds core) - let NonRec var expr = bind + --liftIO $ printBinds (cm_binds core) + let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["full_adder", "half_adder"] + liftIO $ printBinds binds -- Turn bind into VHDL - let vhdl = State.evalState (mkVHDL bind) (VHDLSession 0 builtin_funcs) - liftIO $ putStr $ showSDoc $ ppr expr - liftIO $ putStr "\n\n" - liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr $ vhdl - return expr + let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 []) + liftIO $ putStr $ concat $ map (render . ForSyDe.Backend.Ppr.ppr) vhdl + return () where -- Turns the given bind into VHDL - mkVHDL bind = do - -- Get the function signature - (name, f) <- mkHWFunction bind - -- Add it to the session - addFunc name f - arch <- getArchitecture bind - return arch + mkVHDL binds = do + -- Add the builtin functions + mapM (uncurry addFunc) builtin_funcs + -- Get the function signatures + funcs <- mapM mkHWFunction binds + -- Add them to the session + mapM (uncurry addFunc) funcs + -- Create architectures for them + mapM getArchitecture binds printTarget (Target (TargetFile file (Just x)) obj Nothing) = print $ show file @@ -78,18 +81,18 @@ printBind (Rec binds) = do printBind' (b, expr) = do putStr $ getOccString b - --putStr $ showSDoc $ ppr expr + putStr $ showSDoc $ ppr expr putStr "\n" -findBind :: String -> [CoreBind] -> CoreBind -findBind lookfor = +findBind :: [CoreBind] -> String -> Maybe CoreBind +findBind binds lookfor = -- This ignores Recs and compares the name of the bind with lookfor, -- disregarding any namespaces in OccName and extra attributes in Name and -- Var. - Maybe.fromJust . find (\b -> case b of + find (\b -> case b of Rec l -> False NonRec var _ -> lookfor == (occNameString $ nameOccName $ getName var) - ) + ) binds getPortMapEntry :: SignalNameMap AST.VHDLId -- The port name to bind to @@ -165,7 +168,7 @@ getInstantiations args outs binds app@(App expr arg) = do -- This is an normal function application, which maps to a component -- instantiation. -- Lookup the hwfunction to instantiate - HWFunction inports outport <- getHWFunc name + HWFunction vhdl_id inports outport <- getHWFunc name -- Generate a unique name for the application appname <- uniqueName "app" -- Expand each argument to a signal or port name, possibly generating @@ -178,7 +181,7 @@ getInstantiations args outs binds app@(App expr arg) = do -- Build and return a component instantiation let comp = AST.CompInsSm (AST.unsafeVHDLBasicId appname) - (AST.IUEntity (AST.NSimple (AST.unsafeVHDLBasicId name))) + (AST.IUEntity (AST.NSimple vhdl_id)) (AST.PMapAspect (inmaps ++ outmaps)) return (sigs, (AST.CSISm comp) : comps) @@ -197,20 +200,24 @@ expandExpr :: -- the expression's arguments SignalNameMap AST.VHDLId) -- The signal names corresponding to -- the expression's result. -expandExpr binds (Lam b expr) = do +expandExpr binds lam@(Lam b expr) = do -- Generate a new signal to which we will expect this argument to be bound. signal_name <- uniqueName ("arg-" ++ getOccString b) - -- TODO: This uses the bit type hardcoded - let (signal_id, signal_decl) = mkSignal signal_name vhdl_bit_ty + -- Find the type of the binder + let (arg_ty, _) = Type.splitFunTy (CoreUtils.exprType lam) + -- Create signal names for the binder + let arg_signal = getPortNameMapForTy ("xxx") arg_ty + -- Create the corresponding signal declarations + let signal_decls = mkSignalsFromMap arg_signal -- Add the binder to the list of binds - let binds' = (b, Signal signal_id) : binds + let binds' = (b, arg_signal) : binds -- Expand the rest of the expression - (signal_decls, statements, arg_signals, res_signal) <- expandExpr binds' expr + (signal_decls', statements', arg_signals', res_signal') <- expandExpr binds' expr -- Properly merge the results - return (signal_decl : signal_decls, - statements, - (Signal signal_id) : arg_signals, - res_signal) + return (signal_decls ++ signal_decls', + statements', + arg_signal : arg_signals', + res_signal') expandExpr binds (Var id) = return ([], [], [], Signal signal_id) @@ -220,6 +227,16 @@ expandExpr binds (Var id) = (error $ "Argument " ++ getOccString id ++ "is unknown") (lookup id binds) +expandExpr binds l@(Let (NonRec b bexpr) expr) = do + (signal_decls, statements, arg_signals, res_signals) <- expandExpr binds bexpr + let binds' = (b, res_signals) : binds + (signal_decls', statements', arg_signals', res_signals') <- expandExpr binds' expr + return ( + signal_decls ++ signal_decls', + statements ++ statements', + arg_signals', + res_signals') + expandExpr binds app@(App _ _) = do let ((Var f), args) = collectArgs app if isTupleConstructor f @@ -228,6 +245,14 @@ expandExpr binds app@(App _ _) = do else expandApplicationExpr binds (CoreUtils.exprType app) f args +expandExpr binds expr@(Case (Var v) b _ alts) = + case alts of + [alt] -> expandSingleAltCaseExpr binds v b alt + otherwise -> error $ "Multiple alternative case expression not supported: " ++ (showSDoc $ ppr expr) + +expandExpr binds expr@(Case _ b _ _) = + error $ "Case expression with non-variable scrutinee not supported: " ++ (showSDoc $ ppr expr) + expandExpr binds expr = error $ "Unsupported expression: " ++ (showSDoc $ ppr $ expr) @@ -238,8 +263,55 @@ expandBuildTupleExpr :: -> [CoreExpr] -- A list of expressions to put in the tuple -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap AST.VHDLId], SignalNameMap AST.VHDLId) -- See expandExpr -expandBuildTupleExpr binds args = - error $ "Tuple construction not supported" +expandBuildTupleExpr binds args = do + -- Split the tuple constructor arguments into types and actual values. + let (_, vals) = splitTupleConstructorArgs args + -- Expand each of the values in the tuple + (signals_declss, statementss, arg_signalss, res_signals) <- + (Monad.liftM List.unzip4) $ mapM (expandExpr binds) vals + if any (not . null) arg_signalss + then error "Putting high order functions in tuples not supported" + else + return ( + concat signals_declss, + concat statementss, + [], + Tuple res_signals) + +-- Expands the most simple case expression that scrutinizes a plain variable +-- and has a single alternative. This simple form currently allows only for +-- unpacking tuple variables. +expandSingleAltCaseExpr :: + [(CoreBndr, SignalNameMap AST.VHDLId)] + -- A list of bindings in effect + -> Var.Var -- The scrutinee + -> CoreBndr -- The binder to bind the scrutinee to + -> CoreAlt -- The single alternative + -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap AST.VHDLId], SignalNameMap AST.VHDLId) + -- See expandExpr + +expandSingleAltCaseExpr binds v b alt@(DataAlt datacon, bind_vars, expr) = + if not (DataCon.isTupleCon datacon) + then + error $ "Dataconstructors other than tuple constructors not supported in case pattern of alternative: " ++ (showSDoc $ ppr alt) + else + let + -- Lookup the scrutinee (which must be a variable bound to a tuple) in + -- the existing bindings list and get the portname map for each of + -- it's elements. + Tuple tuple_ports = Maybe.fromMaybe + (error $ "Case expression uses unknown scrutinee " ++ getOccString v) + (lookup v binds) + -- TODO include b in the binds list + -- Merge our existing binds with the new binds. + binds' = (zip bind_vars tuple_ports) ++ binds + in + -- Expand the expression with the new binds list + expandExpr binds' expr + +expandSingleAltCaseExpr _ _ _ alt = + error $ "Case patterns other than data constructors not supported in case alternative: " ++ (showSDoc $ ppr alt) + -- Expands the application of argument to a function into VHDL expandApplicationExpr :: @@ -255,7 +327,7 @@ expandApplicationExpr binds ty f args = do -- Generate a unique name for the application appname <- uniqueName ("app-" ++ name) -- Lookup the hwfunction to instantiate - HWFunction inports outport <- getHWFunc name + HWFunction vhdl_id inports outport <- getHWFunc name -- Expand each of the args, so each of them is reduced to output signals (arg_signal_decls, arg_statements, arg_res_signals) <- expandArgs binds args -- Bind each of the input ports to the expanded arguments @@ -269,7 +341,7 @@ expandApplicationExpr binds ty f args = do -- Instantiate the component let component = AST.CSISm $ AST.CompInsSm (AST.unsafeVHDLBasicId appname) - (AST.IUEntity (AST.NSimple (AST.unsafeVHDLBasicId name))) + (AST.IUEntity (AST.NSimple vhdl_id)) (AST.PMapAspect (inmaps ++ outmaps)) -- Merge the generated declarations return ( @@ -359,6 +431,8 @@ splitTupleConstructorArgs (e:es) = where (tys, vals) = splitTupleConstructorArgs es +splitTupleConstructorArgs [] = ([], []) + mapOutputPorts :: SignalNameMap AST.VHDLId -- The output portnames of the component -> SignalNameMap AST.VHDLId -- The output portnames and/or signals to map these to @@ -381,18 +455,17 @@ getArchitecture (Rec _) = error "Recursive binders not supported" getArchitecture (NonRec var expr) = do let name = (getOccString var) - HWFunction inports outport <- getHWFunc name + HWFunction vhdl_id inports outport <- getHWFunc name sess <- State.get (signal_decls, statements, arg_signals, res_signal) <- expandExpr [] expr let inport_assigns = concat $ zipWith createSignalAssignments arg_signals inports let outport_assigns = createSignalAssignments outport res_signal return $ AST.ArchBody (AST.unsafeVHDLBasicId "structural") - -- Use unsafe for now, to prevent pulling in ForSyDe error handling - (AST.NSimple (AST.unsafeVHDLBasicId name)) + (AST.NSimple vhdl_id) (map AST.BDISD signal_decls) (inport_assigns ++ outport_assigns ++ statements) - + -- Create concurrent assignments of one map of signals to another. The maps -- should have a similar form. createSignalAssignments :: @@ -414,6 +487,9 @@ createSignalAssignments (Signal dst) (Signal src) = createSignalAssignments (Tuple dsts) (Tuple srcs) = concat $ zipWith createSignalAssignments dsts srcs +createSignalAssignments dst src = + error $ "Non matching source and destination: " ++ show dst ++ "\nand\n" ++ show src + data SignalNameMap t = Tuple [SignalNameMap t] | Signal t @@ -438,6 +514,7 @@ getPortNameMapForTy name ty = (tycon, args) = Type.splitTyConApp ty data HWFunction = HWFunction { -- A function that is available in hardware + vhdlId :: AST.VHDLId, inPorts :: [SignalNameMap AST.VHDLId], outPort :: SignalNameMap AST.VHDLId --entity :: AST.EntityDec @@ -450,9 +527,9 @@ mkHWFunction :: -> VHDLState (String, HWFunction) -- The name of the function and its interface mkHWFunction (NonRec var expr) = - return (name, HWFunction inports outport) + return (name, HWFunction (mkVHDLId name) inports outport) where - name = (getOccString var) + name = getOccString var ty = CoreUtils.exprType expr (fargs, res) = Type.splitFunTys ty args = if length fargs == 1 then fargs else (init fargs) @@ -503,9 +580,10 @@ mkVHDLId = AST.unsafeVHDLBasicId builtin_funcs = [ - ("hwxor", HWFunction [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")), - ("hwand", HWFunction [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")), - ("hwnot", HWFunction [Signal $ mkVHDLId "i"] (Signal $ mkVHDLId "o")) + ("hwxor", HWFunction (mkVHDLId "hwxor") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")), + ("hwand", HWFunction (mkVHDLId "hwand") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")), + ("hwor", HWFunction (mkVHDLId "hwor") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")), + ("hwnot", HWFunction (mkVHDLId "hwnot") [Signal $ mkVHDLId "i"] (Signal $ mkVHDLId "o")) ] vhdl_bit_ty :: AST.TypeMark