X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=6a784251d3c310240fc657b8a0c183980cc80202;hb=d3a445954d4e2f93ff64839f4db72e7541b69a86;hp=841f63b892c2f330adfa88bca5c837cf5a7ada23;hpb=6a57a063a1765dea8e72628d59efaaa5ecfa66e1;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 841f63b..6a78425 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -92,9 +92,10 @@ moduleToVHDL core list = do
       -- Create entities and architectures for them
       Monad.zipWithM processBind statefuls binds
       modFuncs nameFlatFunction
-      modFuncs VHDL.createEntity
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
       modFuncs VHDL.createArchitecture
-      VHDL.getDesignFiles
+      funcs <- getFuncs
+      return $ VHDL.getDesignFiles (map snd funcs)
 
 -- | Write the given design file to a file inside the given dir
 --   The first library unit in the designfile must be an entity, whose name
@@ -387,7 +388,7 @@ addBuiltIn (BuiltIn name args res) = do
     setEntity hsfunc entity
   where
     hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
-    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing
 
 builtin_funcs = 
   [