X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=64e009e79db6ec6460dd88cbf45b2035a352c79e;hb=e96a41a863669f7828fca0f5c4b7c3aced9261a1;hp=1fefc6e2fe553cdaa9c1219866dda8ffcbf27509;hpb=5915de9ec972ca50bd9eb111cddc0fc55aff51ac;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index 1fefc6e..64e009e 100644 --- a/Translator.hs +++ b/Translator.hs @@ -8,6 +8,7 @@ import qualified TyCon import qualified DataCon import qualified Maybe import qualified Module +import qualified Control.Monad.State as State import Name import Data.Generics import NameEnv ( lookupNameEnv ) @@ -42,10 +43,21 @@ main = liftIO $ printBinds (cm_binds core) let bind = findBind "half_adder" (cm_binds core) let NonRec var expr = bind + -- Turn bind into VHDL + let vhdl = State.evalState (mkVHDL bind) (VHDLSession 0 builtin_funcs) liftIO $ putStr $ showSDoc $ ppr expr liftIO $ putStr "\n\n" - liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr $ getArchitecture bind + liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr $ vhdl return expr + where + -- Turns the given bind into VHDL + mkVHDL bind = do + -- Get the function signature + (name, f) <- mkHWFunction bind + -- Add it to the session + addFunc name f + arch <- getArchitecture bind + return arch printTarget (Target (TargetFile file (Just x)) obj Nothing) = print $ show file @@ -81,7 +93,7 @@ findBind lookfor = -- Accepts a port name and an argument to map to it. -- Returns the appropriate line for in the port map -getPortMapEntry binds portname (Var id) = +getPortMapEntry binds (Port portname) (Var id) = (Just (AST.unsafeVHDLBasicId portname)) AST.:=>: (AST.ADName (AST.NSimple (AST.unsafeVHDLBasicId signalname))) where Port signalname = Maybe.fromMaybe @@ -91,17 +103,16 @@ getPortMapEntry binds portname (Var id) = getPortMapEntry binds _ a = error $ "Unsupported argument: " ++ (showSDoc $ ppr a) getInstantiations :: - PortNameMap -- The arguments that need to be applied to the - -- expression. Should always be the Args - -- constructor. + [PortNameMap] -- The arguments that need to be applied to the + -- expression. -> PortNameMap -- The output ports that the expression should generate. -> [(CoreBndr, PortNameMap)] -- A list of bindings in effect -> CoreSyn.CoreExpr -- The expression to generate an architecture for - -> [AST.ConcSm] -- The resulting VHDL code + -> VHDLState [AST.ConcSm] -- The resulting VHDL code -- A lambda expression binds the first argument (a) to the binder b. -getInstantiations (Args (a:as)) outs binds (Lam b expr) = - getInstantiations (Args as) outs ((b, a):binds) expr +getInstantiations (a:as) outs binds (Lam b expr) = + getInstantiations as outs ((b, a):binds) expr -- A case expression that checks a single variable and has a single -- alternative, can be used to take tuples apart @@ -123,27 +134,27 @@ getInstantiations args outs binds (Case (Var v) b _ [res]) = (lookup v binds) -- An application is an instantiation of a component -getInstantiations args outs binds app@(App expr arg) = - if isTupleConstructor f then - let - Tuple outports = outs - (tys, vals) = splitTupleConstructorArgs fargs - in - concat $ zipWith +getInstantiations args outs binds app@(App expr arg) = do + let ((Var f), fargs) = collectArgs app + name = getOccString f + if isTupleConstructor f + then do + let Tuple outports = outs + (tys, vals) = splitTupleConstructorArgs fargs + insts <- sequence $ zipWith (\outs' expr' -> getInstantiations args outs' binds expr') outports vals - else - [AST.CSISm comp] - where - ((Var f), fargs) = collectArgs app - comp = AST.CompInsSm - (AST.unsafeVHDLBasicId "app") - (AST.IUEntity (AST.NSimple (AST.unsafeVHDLBasicId compname))) - (AST.PMapAspect ports) - compname = getOccString f - ports = - zipWith (getPortMapEntry binds) ["portin0", "portin1"] fargs - ++ mapOutputPorts (Port "portout") outs + return $ concat insts + else do + HWFunction inports outport <- getHWFunc name + let comp = AST.CompInsSm + (AST.unsafeVHDLBasicId "app") + (AST.IUEntity (AST.NSimple (AST.unsafeVHDLBasicId name))) + (AST.PMapAspect ports) + ports = + zipWith (getPortMapEntry binds) inports fargs + ++ mapOutputPorts outport outs + return [AST.CSISm comp] getInstantiations args outs binds expr = error $ "Unsupported expression" ++ (showSDoc $ ppr $ expr) @@ -186,33 +197,26 @@ mapOutputPorts (Tuple ports) (Tuple signals) = getArchitecture :: CoreBind -- The binder to expand into an architecture - -> AST.ArchBody -- The resulting architecture + -> VHDLState AST.ArchBody -- The resulting architecture getArchitecture (Rec _) = error "Recursive binders not supported" -getArchitecture (NonRec var expr) = - AST.ArchBody +getArchitecture (NonRec var expr) = do + let name = (getOccString var) + HWFunction inports outport <- getHWFunc name + sess <- State.get + insts <- getInstantiations inports outport [] expr + return $ AST.ArchBody (AST.unsafeVHDLBasicId "structural") -- Use unsafe for now, to prevent pulling in ForSyDe error handling (AST.NSimple (AST.unsafeVHDLBasicId name)) [] - (getInstantiations (Args inportnames) outport [] expr) - where - name = (getOccString var) - ty = CoreUtils.exprType expr - (fargs, res) = Type.splitFunTys ty - --state = if length fargs == 1 then () else (last fargs) - ports = if length fargs == 1 then fargs else (init fargs) - inportnames = case ports of - [port] -> [getPortNameMapForTy "portin" port] - ps -> getPortNameMapForTys "portin" 0 ps - outport = getPortNameMapForTy "portout" res + (insts) data PortNameMap = - Args [PortNameMap] -- Each of the submaps represent an argument to the - -- function. Should only occur at top level. - | Tuple [PortNameMap] + Tuple [PortNameMap] | Port String + deriving (Show) -- Generate a port name map (or multiple for tuple types) in the given direction for -- each type given. @@ -231,3 +235,60 @@ getPortNameMapForTy name ty = Port name where (tycon, args) = Type.splitTyConApp ty + +data HWFunction = HWFunction { -- A function that is available in hardware + inPorts :: [PortNameMap], + outPort :: PortNameMap + --entity :: AST.EntityDec +} deriving (Show) + +-- Turns a CoreExpr describing a function into a description of its input and +-- output ports. +mkHWFunction :: + CoreBind -- The core binder to generate the interface for + -> VHDLState (String, HWFunction) -- The name of the function and its interface + +mkHWFunction (NonRec var expr) = + return (name, HWFunction inports outport) + where + name = (getOccString var) + ty = CoreUtils.exprType expr + (fargs, res) = Type.splitFunTys ty + args = if length fargs == 1 then fargs else (init fargs) + --state = if length fargs == 1 then () else (last fargs) + inports = case args of + -- Handle a single port specially, to prevent an extra 0 in the name + [port] -> [getPortNameMapForTy "portin" port] + ps -> getPortNameMapForTys "portin" 0 ps + outport = getPortNameMapForTy "portout" res + +mkHWFunction (Rec _) = + error "Recursive binders not supported" + +data VHDLSession = VHDLSession { + nameCount :: Int, -- A counter that can be used to generate unique names + funcs :: [(String, HWFunction)] -- All functions available, indexed by name +} deriving (Show) + +type VHDLState = State.State VHDLSession + +-- Add the function to the session +addFunc :: String -> HWFunction -> VHDLState () +addFunc name f = do + fs <- State.gets funcs -- Get the funcs element from the session + State.modify (\x -> x {funcs = (name, f) : fs }) -- Prepend name and f + +-- Lookup the function with the given name in the current session. Errors if +-- it was not found. +getHWFunc :: String -> VHDLState HWFunction +getHWFunc name = do + fs <- State.gets funcs -- Get the funcs element from the session + return $ Maybe.fromMaybe + (error $ "Function " ++ name ++ "is unknown? This should not happen!") + (lookup name fs) + +builtin_funcs = + [ + ("hwxor", HWFunction [Port "a", Port "b"] (Port "o")), + ("hwand", HWFunction [Port "a", Port "b"] (Port "o")) + ]