X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=5e36b3856b631666cc4fb62fb932631e21a33943;hb=bf0b6fedf46d525cc7e4d389b4fb7dd539174939;hp=383c477282e04fa3429c153520cf13064eca1d0d;hpb=0de275199ba2f3a98339eefb7784e061a451c5f7;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 383c477..5e36b38 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -94,7 +94,8 @@ moduleToVHDL core list = do
       modFuncs nameFlatFunction
       modFuncs VHDL.createEntity
       modFuncs VHDL.createArchitecture
-      VHDL.getDesignFiles
+      funcs <- getFuncs
+      return $ VHDL.getDesignFiles (map snd funcs)
 
 -- | Write the given design file to a file inside the given dir
 --   The first library unit in the designfile must be an entity, whose name