X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=53befc228e6ef947107b72141d9cb7c713fd5606;hb=f476ee837aaea76011f8e47e1181e4a09ec86555;hp=3cf456e0ea6118145796430b19d0487c24f630d9;hpb=77ce22fc9dc9cab9afe56b5a093590359e38e5cb;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 3cf456e..53befc2 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -49,6 +49,15 @@ main = do
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
+-- | Show the core structure of the given binds in the given file.
+listBind :: String -> String -> IO ()
+listBind filename name = do
+  core <- loadModule filename
+  let binds = findBinds core [name]
+  putStr "\n"
+  putStr $ prettyShow binds
+  putStr "\n\n"
+
 -- | Translate the binds with the given names from the given core module to
 --   VHDL
 moduleToVHDL :: HscTypes.CoreModule -> [String] -> IO AST.DesignFile