X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=4992d1cca7910940f4c1cfc6cc22cdf686ca143b;hb=a628d8d874df6af54c6d4f766012bac117eea037;hp=13c0ac7bcadff4732cebed3608c46c61e228ae44;hpb=0ebb1e486484787bbf1c923f4d0006044a827632;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index 13c0ac7..4992d1c 100644 --- a/Translator.hs +++ b/Translator.hs @@ -26,6 +26,7 @@ import qualified Monad -- ForSyDe to get access to these modules. import qualified ForSyDe.Backend.VHDL.AST as AST import qualified ForSyDe.Backend.VHDL.Ppr +import qualified ForSyDe.Backend.VHDL.FileIO import qualified ForSyDe.Backend.Ppr -- This is needed for rendering the pretty printed VHDL import Text.PrettyPrint.HughesPJ (render) @@ -49,6 +50,7 @@ main = -- Turn bind into VHDL let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 []) liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl + liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl" return () where -- Turns the given bind into VHDL @@ -206,7 +208,7 @@ expandExpr :: -- the expression's result. expandExpr binds lam@(Lam b expr) = do -- Generate a new signal to which we will expect this argument to be bound. - signal_name <- uniqueName ("arg-" ++ getOccString b) + signal_name <- uniqueName ("arg_" ++ getOccString b) -- Find the type of the binder let (arg_ty, _) = Type.splitFunTy (CoreUtils.exprType lam) -- Create signal names for the binder @@ -329,7 +331,7 @@ expandApplicationExpr :: expandApplicationExpr binds ty f args = do let name = getOccString f -- Generate a unique name for the application - appname <- uniqueName ("app-" ++ name) + appname <- uniqueName ("app_" ++ name) -- Lookup the hwfunction to instantiate HWFunction vhdl_id inports outport <- getHWFunc name -- Expand each of the args, so each of them is reduced to output signals @@ -337,7 +339,7 @@ expandApplicationExpr binds ty f args = do -- Bind each of the input ports to the expanded arguments let inmaps = concat $ zipWith createAssocElems inports arg_res_signals -- Create signal names for our result - let res_signal = getPortNameMapForTy (appname ++ "-out") ty + let res_signal = getPortNameMapForTy (appname ++ "_out") ty -- Create the corresponding signal declarations let signal_decls = mkSignalsFromMap res_signal -- Bind each of the output ports to our output signals @@ -594,7 +596,7 @@ uniqueName :: String -> VHDLState String uniqueName name = do count <- State.gets nameCount -- Get the funcs element from the session State.modify (\s -> s {nameCount = count + 1}) - return $ name ++ "-" ++ (show count) + return $ name ++ "_" ++ (show count) -- Shortcut mkVHDLId :: String -> AST.VHDLId