X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=2a752a79d34c94cc5ccc4b32cc296b7aaeade5d2;hb=059c20c7b953a21097939a47ecac7f6cad05541a;hp=383c477282e04fa3429c153520cf13064eca1d0d;hpb=0de275199ba2f3a98339eefb7784e061a451c5f7;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index 383c477..2a752a7 100644 --- a/Translator.hs +++ b/Translator.hs @@ -91,10 +91,12 @@ moduleToVHDL core list = do mapM addBuiltIn builtin_funcs -- Create entities and architectures for them Monad.zipWithM processBind statefuls binds - modFuncs nameFlatFunction - modFuncs VHDL.createEntity - modFuncs VHDL.createArchitecture - VHDL.getDesignFiles + modFuncMap $ Map.map (\fdata -> fdata {flatFunc = fmap nameFlatFunction (flatFunc fdata)}) + modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata}) + funcs <- getFuncMap + modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcArch = VHDL.createArchitecture funcs hsfunc fdata}) + funcs <- getFuncs + return $ VHDL.getDesignFiles (map snd funcs) -- | Write the given design file to a file inside the given dir -- The first library unit in the designfile must be an entity, whose name @@ -331,21 +333,15 @@ mkHsFunction f ty stateful= -- | Adds signal names to the given FlatFunction nameFlatFunction :: - HsFunction - -> FuncData - -> VHDLState () + FlatFunction + -> FlatFunction -nameFlatFunction hsfunc fdata = - let func = flatFunc fdata in - case func of - -- Skip (builtin) functions without a FlatFunction - Nothing -> do return () - -- Name the signals in all other functions - Just flatfunc -> - let s = flat_sigs flatfunc in - let s' = map nameSignal s in - let flatfunc' = flatfunc { flat_sigs = s' } in - setFlatFunc hsfunc flatfunc' +nameFlatFunction flatfunc = + -- Name the signals + let + s = flat_sigs flatfunc + s' = map nameSignal s in + flatfunc { flat_sigs = s' } where nameSignal :: (SignalId, SignalInfo) -> (SignalId, SignalInfo) nameSignal (id, info) =