X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=1b2d24bf13aac610423c22983bd18373519c36ff;hb=43f37e2590806f2f1019018dfc7274a428ece743;hp=a01fa3221a7f508917a5e41c76a8aaac62a3c4b1;hpb=997431255f0345a9785a762fe6193751fae90651;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index a01fa32..1b2d24b 100644 --- a/Translator.hs +++ b/Translator.hs @@ -17,6 +17,14 @@ import Outputable ( showSDoc, ppr ) import GHC.Paths ( libdir ) import DynFlags ( defaultDynFlags ) import List ( find ) +-- The following modules come from the ForSyDe project. They are really +-- internal modules, so ForSyDe.cabal has to be modified prior to installing +-- ForSyDe to get access to these modules. +import qualified ForSyDe.Backend.VHDL.AST as AST +import qualified ForSyDe.Backend.VHDL.Ppr +import qualified ForSyDe.Backend.Ppr +-- This is needed for rendering the pretty printed VHDL +import Text.PrettyPrint.HughesPJ (render) main = do @@ -34,9 +42,10 @@ main = liftIO $ printBinds (cm_binds core) let bind = findBind "half_adder" (cm_binds core) let NonRec var expr = bind + let sess = VHDLSession 0 builtin_funcs liftIO $ putStr $ showSDoc $ ppr expr liftIO $ putStr "\n\n" - liftIO $ putStr $ getArchitecture bind + liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr $ getArchitecture sess bind return expr printTarget (Target (TargetFile file (Just x)) obj Nothing) = @@ -74,7 +83,7 @@ findBind lookfor = -- Accepts a port name and an argument to map to it. -- Returns the appropriate line for in the port map getPortMapEntry binds portname (Var id) = - "\t" ++ portname ++ " => " ++ signalname ++ "\n" + (Just (AST.unsafeVHDLBasicId portname)) AST.:=>: (AST.ADName (AST.NSimple (AST.unsafeVHDLBasicId signalname))) where Port signalname = Maybe.fromMaybe (error $ "Argument " ++ getOccString id ++ "is unknown") @@ -83,25 +92,26 @@ getPortMapEntry binds portname (Var id) = getPortMapEntry binds _ a = error $ "Unsupported argument: " ++ (showSDoc $ ppr a) getInstantiations :: - PortNameMap -- The arguments that need to be applied to the + VHDLSession + -> PortNameMap -- The arguments that need to be applied to the -- expression. Should always be the Args -- constructor. -> PortNameMap -- The output ports that the expression should generate. -> [(CoreBndr, PortNameMap)] -- A list of bindings in effect -> CoreSyn.CoreExpr -- The expression to generate an architecture for - -> String -- The resulting VHDL code + -> [AST.ConcSm] -- The resulting VHDL code -- A lambda expression binds the first argument (a) to the binder b. -getInstantiations (Args (a:as)) outs binds (Lam b expr) = - getInstantiations (Args as) outs ((b, a):binds) expr +getInstantiations sess (Args (a:as)) outs binds (Lam b expr) = + getInstantiations sess (Args as) outs ((b, a):binds) expr -- A case expression that checks a single variable and has a single -- alternative, can be used to take tuples apart -getInstantiations args outs binds (Case (Var v) b _ [res]) = +getInstantiations sess args outs binds (Case (Var v) b _ [res]) = case altcon of DataAlt datacon -> if (DataCon.isTupleCon datacon) then - getInstantiations args outs binds' expr + getInstantiations sess args outs binds' expr else error "Data constructors other than tuples not supported" otherwise -> @@ -115,28 +125,33 @@ getInstantiations args outs binds (Case (Var v) b _ [res]) = (lookup v binds) -- An application is an instantiation of a component -getInstantiations args outs binds app@(App expr arg) = +getInstantiations sess args outs binds app@(App expr arg) = if isTupleConstructor f then let Tuple outports = outs (tys, vals) = splitTupleConstructorArgs fargs in concat $ zipWith - (\outs' expr' -> getInstantiations args outs' binds expr') + (\outs' expr' -> getInstantiations sess args outs' binds expr') outports vals else - --indent ++ "F:\n" ++ (getInstantiations (' ':indent) expr) ++ "\n" ++ indent ++ "A:\n" ++ (getInstantiations (' ':indent) arg) ++ "\n" - "app : " ++ (getOccString f) ++ "\n" - ++ "port map (\n" - -- Map input ports of f - ++ concat (zipWith (getPortMapEntry binds) ["portin0", "portin1"] fargs) - -- Map output ports of f - ++ mapOutputPorts (Port "portout") outs - ++ ");\n" + [AST.CSISm comp] where ((Var f), fargs) = collectArgs app + comp = AST.CompInsSm + (AST.unsafeVHDLBasicId "app") + (AST.IUEntity (AST.NSimple (AST.unsafeVHDLBasicId compname))) + (AST.PMapAspect ports) + compname = getOccString f + hwfunc = Maybe.fromMaybe + (error $ "Function " ++ compname ++ "is unknown") + (lookup compname (funcs sess)) + HWFunction inports outports = hwfunc + ports = + zipWith (getPortMapEntry binds) ["portin0", "portin1"] fargs + ++ mapOutputPorts outports outs -getInstantiations args outs binds expr = +getInstantiations sess args outs binds expr = error $ "Unsupported expression" ++ (showSDoc $ ppr $ expr) -- Is the given name a (binary) tuple constructor @@ -161,20 +176,34 @@ splitTupleConstructorArgs (e:es) = where (tys, vals) = splitTupleConstructorArgs es +mapOutputPorts :: + PortNameMap -- The output portnames of the component + -> PortNameMap -- The output portnames and/or signals to map these to + -> [AST.AssocElem] -- The resulting output ports + -- Map the output port of a component to the output port of the containing -- entity. -mapOutputPorts (Port port) (Port signal) = - "\t" ++ port ++ " => " ++ signal ++ "\n" +mapOutputPorts (Port portname) (Port signalname) = + [(Just (AST.unsafeVHDLBasicId portname)) AST.:=>: (AST.ADName (AST.NSimple (AST.unsafeVHDLBasicId signalname)))] -- Map matching output ports in the tuple mapOutputPorts (Tuple ports) (Tuple signals) = concat (zipWith mapOutputPorts ports signals) -getArchitecture (NonRec var expr) = - "architecture structural of " ++ name ++ " is\n" - ++ "begin\n" - ++ getInstantiations (Args inportnames) outport [] expr - ++ "end structural\n" +getArchitecture :: + VHDLSession + -> CoreBind -- The binder to expand into an architecture + -> AST.ArchBody -- The resulting architecture + +getArchitecture sess (Rec _) = error "Recursive binders not supported" + +getArchitecture sess (NonRec var expr) = + AST.ArchBody + (AST.unsafeVHDLBasicId "structural") + -- Use unsafe for now, to prevent pulling in ForSyDe error handling + (AST.NSimple (AST.unsafeVHDLBasicId name)) + [] + (getInstantiations sess (Args inportnames) outport [] expr) where name = (getOccString var) ty = CoreUtils.exprType expr @@ -209,3 +238,20 @@ getPortNameMapForTy name ty = Port name where (tycon, args) = Type.splitTyConApp ty + +data HWFunction = HWFunction { -- A function that is available in hardware + inPorts :: PortNameMap, + outPorts :: PortNameMap + --entity :: AST.EntityDec +} + +data VHDLSession = VHDLSession { + nameCount :: Int, -- A counter that can be used to generate unique names + funcs :: [(String, HWFunction)] -- All functions available, indexed by name +} + +builtin_funcs = + [ + ("hwxor", HWFunction (Args [Port "a", Port "b"]) (Port "o")), + ("hwand", HWFunction (Args [Port "a", Port "b"]) (Port "o")) + ]