X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=1a753c2d52b592af9dbc50811bf90b5330f35702;hb=6b3da07384004751bc64ef88429f452dfe1cee45;hp=3cf456e0ea6118145796430b19d0487c24f630d9;hpb=77ce22fc9dc9cab9afe56b5a093590359e38e5cb;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 3cf456e..1a753c2 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,13 +42,27 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "register_bank"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
+-- | Show the core structure of the given binds in the given file.
+listBind :: String -> String -> IO ()
+listBind filename name = do
+  core <- loadModule filename
+  let binds = findBinds core [name]
+  putStr "\n"
+  putStr $ prettyShow binds
+  putStr $ showSDoc $ ppr binds
+  putStr "\n\n"
+
 -- | Translate the binds with the given names from the given core module to
 --   VHDL
 moduleToVHDL :: HscTypes.CoreModule -> [String] -> IO AST.DesignFile