X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Translator.hs;h=0f60277671f99b646ec427deb8fd82ce92d53169;hb=e230d86ae7135a268a72cdffba947a9011001ec2;hp=3f60330b37a68b8680cdedec20996f28134c5a42;hpb=3fb6a3a819f85d89853660347b42f6085d20fb57;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 3f60330..0f60277 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -52,8 +52,8 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
-main = do
-  makeVHDL "Adders.hs" "highordtest" True
+-- main = do
+--   makeVHDL "Alu.hs" "exec" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
@@ -62,7 +62,7 @@ makeVHDL filename name stateful = do
   -- Translate to VHDL
   vhdl <- moduleToVHDL core [(name, stateful)]
   -- Write VHDL to file
-  let dir = "../vhdl/vhdl/" ++ name ++ "/"
+  let dir = "./vhdl/" ++ name ++ "/"
   mapM (writeVHDL dir) vhdl
   return ()