X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Pretty.hs;h=78876b30127b835e314dfcf4493edf77d69d6d01;hb=472a96af53dd624ba526ab86f250ac8f88a152ef;hp=22862d59a0f256f16f87bfd0aeef87051b0c7f8c;hpb=1de7e7d5eb0c3fd3be4a348e10fec91c7f3d029d;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Pretty.hs b/Pretty.hs
index 22862d5..78876b3 100644
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -7,9 +7,13 @@ import qualified HscTypes
 import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
+import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.AST as AST
+
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
+import VHDLTypes
 
 instance Pretty HsFunction where
   pPrint (HsFunction name args res) =
@@ -28,11 +32,12 @@ instance Pretty HsValueUse where
   pPrint (HighOrder _ _) = text "Higher Order"
 
 instance Pretty id => Pretty (FlatFunction' id) where
-  pPrint (FlatFunction args res apps conds) =
+  pPrint (FlatFunction args res apps conds sigs) =
     (text "Args: ") $$ nest 10 (pPrint args)
     $+$ (text "Result: ") $$ nest 10 (pPrint res)
     $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps))
     $+$ (text "Conds: ") $$ nest 10 (pPrint conds)
+    $+$ text "Signals: " $$ nest 10 (pPrint sigs)
 
 instance Pretty id => Pretty (FApp id) where
   pPrint (FApp func args res) =
@@ -41,22 +46,51 @@ instance Pretty id => Pretty (FApp id) where
 instance Pretty id => Pretty (CondDef id) where
   pPrint _ = text "TODO"
 
+instance Pretty SignalInfo where
+  pPrint (SignalInfo Nothing ty) = empty
+  pPrint (SignalInfo (Just name) ty) = text ":" <> text name
+
 instance Pretty VHDLSession where
   pPrint (VHDLSession mod nameCount funcs) =
     text "Module: " $$ nest 15 (text modname)
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc)) =
-        pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (pPrint flatfunc))
+      ppfunc (hsfunc, fdata) =
+        pPrint hsfunc $+$ nest 5 (pPrint fdata)
       modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
 
+instance Pretty FuncData where
+  pPrint (FuncData flatfunc entity arch) =
+    text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+    $+$ text "Entity" $$ nest 15 (ppent entity)
+    $+$ pparch arch
+    where
+      ppffunc (Just f) = pPrint f
+      ppffunc Nothing  = text "Nothing"
+      ppent (Just e)   = pPrint e
+      ppent Nothing    = text "Nothing"
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
+
+instance Pretty Entity where
+  pPrint (Entity args res decl) =
+    text "Args: " $$ nest 10 (pPrint args)
+    $+$ text "Result: " $$ nest 10 (pPrint res)
+    $+$ ppdecl decl
+    where
+      ppdecl Nothing = text "VHDL entity not present"
+      ppdecl (Just _) = text "VHDL entity present"
+
 instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
     text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
 
+instance Pretty AST.VHDLId where
+  pPrint id = ForSyDe.Backend.Ppr.ppr id
+
 prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'