X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Pretty.hs;h=561cfb10d489c113f3a2b9d48527847c7d39eb9e;hb=7a5b4eb318626f327dd6b0d69e99a8247f56399c;hp=d4ed8f01d93da2ddcc46be08d6c5f83eed1db487;hpb=9913c8098b3f42e404ee1b76c2ccd47f15769c64;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Pretty.hs b/Pretty.hs
index d4ed8f0..561cfb1 100644
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -7,9 +7,13 @@ import qualified HscTypes
 import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
+import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.AST as AST
+
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
+import VHDLTypes
 
 instance Pretty HsFunction where
   pPrint (HsFunction name args res) =
@@ -43,8 +47,8 @@ instance Pretty id => Pretty (CondDef id) where
   pPrint _ = text "TODO"
 
 instance Pretty SignalInfo where
-  pPrint (SignalInfo Nothing) = empty
-  pPrint (SignalInfo (Just name)) = text ":" <> text name
+  pPrint (SignalInfo Nothing ty) = empty
+  pPrint (SignalInfo (Just name) ty) = text ":" <> text name
 
 instance Pretty VHDLSession where
   pPrint (VHDLSession mod nameCount funcs) =
@@ -52,18 +56,36 @@ instance Pretty VHDLSession where
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc)) =
+      ppfunc (hsfunc, (FuncData flatfunc entity arch)) =
         pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
+        $+$ (text "Entity") $$ nest 15 (ppent entity)
+        $+$ pparch arch
       ppffunc (Just f) = pPrint f
       ppffunc Nothing  = text "Nothing"
+      ppent (Just e)   = pPrint e
+      ppent Nothing    = text "Nothing"
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
       modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
 
+instance Pretty Entity where
+  pPrint (Entity args res decl) =
+    text "Args: " $$ nest 10 (pPrint args)
+    $+$ text "Result: " $$ nest 10 (pPrint res)
+    $+$ ppdecl decl
+    where
+      ppdecl Nothing = text "VHDL entity not present"
+      ppdecl (Just _) = text "VHDL entity present"
+
 instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
     text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
 
+instance Pretty AST.VHDLId where
+  pPrint id = ForSyDe.Backend.Ppr.ppr id
+
 prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'