X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Pretty.hs;h=2bf57f761541e3280bec0a32175c78a12d81b344;hb=b2a68b424663d5a909791080c416a54088321936;hp=bb62591007c64b089a6476a26815d88c8248f1e6;hpb=289124685555aeb479d5ab238585c5e27346cf09;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Pretty.hs b/Pretty.hs index bb62591..2bf57f7 100644 --- a/Pretty.hs +++ b/Pretty.hs @@ -1,7 +1,19 @@ module Pretty (prettyShow) where +import qualified Data.Map as Map +import qualified CoreSyn +import qualified Module +import qualified HscTypes import Text.PrettyPrint.HughesPJClass -import Flatten +import Outputable ( showSDoc, ppr, Outputable, OutputableBndr) + +import qualified ForSyDe.Backend.Ppr +import qualified ForSyDe.Backend.VHDL.AST as AST + +import HsValueMap +import FlattenTypes +import TranslatorTypes +import VHDLTypes instance Pretty HsFunction where pPrint (HsFunction name args res) = @@ -19,22 +31,70 @@ instance Pretty HsValueUse where pPrint (State n) = char 'C' <> int n pPrint (HighOrder _ _) = text "Higher Order" -instance Pretty FlatFunction where - pPrint (FlatFunction args res apps conds) = +instance Pretty id => Pretty (FlatFunction' id) where + pPrint (FlatFunction args res apps conds sigs) = (text "Args: ") $$ nest 10 (pPrint args) $+$ (text "Result: ") $$ nest 10 (pPrint res) $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps)) $+$ (text "Conds: ") $$ nest 10 (pPrint conds) + $+$ text "Signals: " $$ nest 10 (pPrint sigs) -instance Pretty FApp where +instance Pretty id => Pretty (FApp id) where pPrint (FApp func args res) = pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res -instance Pretty SignalDef where - pPrint (SignalDef id) = pPrint id +instance Pretty id => Pretty (CondDef id) where + pPrint _ = text "TODO" + +instance Pretty SignalInfo where + pPrint (SignalInfo Nothing ty) = empty + pPrint (SignalInfo (Just name) ty) = text ":" <> text name -instance Pretty SignalUse where - pPrint (SignalUse id) = pPrint id +instance Pretty VHDLSession where + pPrint (VHDLSession mod nameCount funcs) = + text "Module: " $$ nest 15 (text modname) + $+$ text "NameCount: " $$ nest 15 (int nameCount) + $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs))) + where + ppfunc (hsfunc, fdata) = + pPrint hsfunc $+$ nest 5 (pPrint fdata) + modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod) -instance Pretty CondDef where - pPrint _ = text "TODO" +instance Pretty FuncData where + pPrint (FuncData flatfunc entity arch) = + text "Flattened: " $$ nest 15 (ppffunc flatfunc) + $+$ text "Entity" $$ nest 15 (ppent entity) + $+$ pparch arch + where + ppffunc (Just f) = pPrint f + ppffunc Nothing = text "Nothing" + ppent (Just e) = pPrint e + ppent Nothing = text "Nothing" + pparch Nothing = text "VHDL architecture not present" + pparch (Just _) = text "VHDL architecture present" + +instance Pretty Entity where + pPrint (Entity id args res decl) = + text "Entity id: " $$ nest 10 (pPrint id) + $+$ text "Args: " $$ nest 10 (pPrint args) + $+$ text "Result: " $$ nest 10 (pPrint res) + $+$ ppdecl decl + where + ppdecl Nothing = text "VHDL entity not present" + ppdecl (Just _) = text "VHDL entity present" + +instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where + pPrint (CoreSyn.NonRec b expr) = + text "NonRec: " $$ nest 10 (prettyBind (b, expr)) + pPrint (CoreSyn.Rec binds) = + text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds) + +instance Pretty AST.VHDLId where + pPrint id = ForSyDe.Backend.Ppr.ppr id + +prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc +prettyBind (b, expr) = + text b' <> text " = " <> text expr' + where + b' = showSDoc $ ppr b + expr' = showSDoc $ ppr expr