X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=PolyAlu.lhs;h=547f0951baa8e27c4f431690603e4470279b653a;hb=f8ca52f68083c6d4081b509681c24b6e059a9eb3;hp=eb97ac332da07d0640e2841364419ce4cc90c6fa;hpb=bf7c294bcfb5b4528e4daf0bdddd18ab59adc86c;p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git

diff --git a/PolyAlu.lhs b/PolyAlu.lhs
index eb97ac3..547f095 100644
--- a/PolyAlu.lhs
+++ b/PolyAlu.lhs
@@ -2,7 +2,7 @@
 %if style == newcode
 \begin{code}
 {-# LANGUAGE  TypeOperators, TypeFamilies, FlexibleContexts #-}
-module PolyCPU where
+module Main where
 
 import qualified Prelude as P
 \end{code}
@@ -12,104 +12,151 @@ import qualified Prelude as P
 \subsection{Introduction}
 \frame
 {
-\frametitle{Small Use Case}
+\frametitle{Small Use Case}\pause
+TODO: Plaatje
 \begin{itemize}
-  \item Small Polymorphic, Higher-Order CPU
-  \item Each function is turned into a hardware component
+  \item Polymorphic, Higher-Order CPU\pause
   \item Use of state will be simple
 \end{itemize}
-}
-
-\frame
-{
-\frametitle{Imports}
-\begin{code}
-import {-"{\color<2>[rgb]{1,0,0}"-}CLasH.HardwareTypes{-"}"-}
-import {-"{\color<3>[rgb]{1,0,0}"-}CLasH.Translator.Annotations{-"}"-}
-\end{code}
+}\note[itemize]{
+\item Small "toy"-example of what can be done in \clash{}
+\item Show what can be translated to Hardware
+\item Put your hardware glasses on: each function will be a component
+\item Use of state will be kept simple
 }
 
 \subsection{Type Definitions}
 \frame
 {
+\frametitle{Type definitions}\pause
+TODO: Plaatje van de ALU
 First we define some ALU types:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
-type Op s a         =   a -> {-"{\color<2>[rgb]{1,0,0}"-}Vector s a{-"}"-} -> a
-type Opcode         =   Bit
+type Op a         =   a -> a -> a
 \end{code}
+\end{beamercolorbox}\pause
+
 And some Register types:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
-type RegBank s a    =   {-"{\color<2>[rgb]{1,0,0}"-}Vector (s :+: D1){-"}"-} a
+type RegBank s a    =   Vector (s :+: D1) a
 type RegState s a   =   State (RegBank s a)
 \end{code}
-And a simple Word type:
-\begin{code}
-type Word           =   {-"{\color<3>[rgb]{1,0,0}"-}SizedInt D12{-"}"-}
-\end{code}
-}
-\subsection{Frameworks for Operations}
-\frame
-{
-We make a primitive operation:
-\begin{code}
-primOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
-primOp f a b = a `f` a
-\end{code}
-We make a vector operation:
-\begin{code}
-vectOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
-vectOp f a b = {-"{\color<2>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
-\end{code}
+\end{beamercolorbox}\pause
+}\note[itemize]{
+\item The first type is already polymorphic in input / output type
+\item State has to be of the State type to be recognized as such
 }
+
 \subsection{Polymorphic, Higher-Order ALU}
 \frame
 {
-We define a polymorphic ALU:
+\frametitle{Simple ALU}
+Abstract ALU definition:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
+type Opcode         =   Bit
 alu :: 
-  Op s a -> 
-  Op s a -> 
-  Opcode -> a -> Vector s a -> a
+  Op a -> Op a -> 
+  Opcode -> a -> a -> a
 alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-}    a b = op1 a b
 alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-}   a b = op2 a b
 \end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item We support Pattern Matching}
+\end{itemize}
+}\note[itemize]{
+\item Alu is both higher-order, and polymorphic
+\item Two parameters are "compile time", others are "runtime"
+\item We support pattern matching
 }
+
 \subsection{Register bank}
 \frame
 {
+\frametitle{Register Bank}
 Make a simple register bank:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
+TODO: Hide type sig
 \begin{code}
 registerBank :: 
-  CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
-  (RegState s a) -> a -> {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} ->
-  {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} -> Bit -> ((RegState s a), a )
+  CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s ->
+  RangedWord s -> Bool -> (RegState s a) -> ((RegState s a), a )
   
-registerBank (State mem) data_in rdaddr wraddr wrenable = 
+registerBank data_in rdaddr wraddr (State mem) = 
   ((State mem'), data_out)
   where
-    data_out  =   mem!rdaddr
-    mem'          {-"{\color<3>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-}  = mem
-                  {-"{\color<3>[rgb]{1,0,0}"-}| otherwise{-"}"-}        = replace mem wraddr data_in
+    data_out  = mem!rdaddr
+    mem'      = replace mem wraddr data_in
 \end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item We support Guards}
+\end{itemize}
+}\note[itemize]{
+\item RangedWord runs from 0 to the upper bound
+\item mem is statefull
+\item We support guards
+\item replace is a builtin function
 }
+
 \subsection{Simple CPU: ALU \& Register Bank}
 \frame
 {
+\frametitle{Simple CPU}
 Combining ALU and register bank:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
+TODO: Hide Instruction type?
 \begin{code}
+type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9) ->  RegState D9 Word ->
 {-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-}
 actual_cpu :: 
-  (Opcode, Word, Vector D4 Word, 
-  RangedWord D9, 
-  RangedWord D9, Bit) -> 
-  RegState D9 Word ->
-  (RegState D9 Word, Word)
+  Instruction -> RegState D9 Word -> (RegState D9 Word, Word)
 
-actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
+actual_cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out)
   where
-    alu_out = alu simpleOp vectorOp opc ram_out b
-    (ram',ram_out)  = registerBank ram a rdaddr wraddr wren
-    simpleOp =  primOp  (+)
-    vectorOp =  vectOp  (+)
+    alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}(+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}(-){-"}"-}) opc d ram_out
+    (ram',ram_out)  = registerBank alu_out rdaddr wraddr ram
 \end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item Annotation is used to indicate top-level component}
+\end{itemize}
+}\note[itemize]{
+\item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us.
+\item the primOp and vectOp frameworks are now supplied with real functionality, the plus (+) operations
+\item No polymorphism or higher-order stuff is allowed at this level.
+\item Functions must be specialized, and have primitives for input and output 
 }
+
+%if style == newcode
+\begin{code}
+ANN(initstate InitState)
+initstate :: RegState D9 Word
+initstate = State (copy (0 :: Word))  
+  
+ANN(program TestInput)
+program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)]
+program =
+  [ (Low, 4, copy (0), 0, 0, High) -- Write 4 to Reg0, out = 0
+  , (Low, 3, copy (0), 0, 1, High) -- Write 3 to Reg1, out = 8
+  , (High,0, copy (3), 1, 0, Low)  -- No Write       , out = 15
+  ]
+
+run func state [] = []
+run func state (i:input) = o:out
+  where
+    (state', o) = func i state
+    out         = run func state' input
+    
+main :: IO ()
+main = do
+  let input = program
+  let istate = initstate
+  let output = run actual_cpu istate input
+  mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output
+  return ()
+\end{code}
+%endif