X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=HighOrdAlu.hs;h=8467c38d92ad815bc55053937a5445aac4a0f01f;hb=699b4f25f903ae9fa7deacf2eeb6204403178de9;hp=cdef7710c206a817b1bedcfa030bdbfefdd6bfe3;hpb=1643800a4ef64501806747d2cafe917be7b1b3b2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs index cdef771..8467c38 100644 --- a/HighOrdAlu.hs +++ b/HighOrdAlu.hs @@ -1,30 +1,31 @@ -module HighOrdAlu where +{-# LANGUAGE TemplateHaskell, ScopedTypeVariables, NoImplicitPrelude #-} -import Prelude hiding ( - null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr, - zipWith, zip, unzip, concat, reverse, iterate ) -import Bits -import Types -import Data.Param.TFVec -import Data.RangedWord +module HighOrdAlu where -constant :: e -> Op D4 e -constant e a b = - e +> (e +> (e +> (e +> empty))) +import qualified Prelude as P +import CLasH.HardwareTypes +import CLasH.Translator.Annotations -inv = hwnot +import HighOrdAluOps -invop :: Op n Bit -invop a b = map inv a +{-# ANN sim_input TestInput#-} +sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))] +sim_input = [ (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) + , (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) + , (Low, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) ] -type Op n e = (TFVec n e -> TFVec n e -> TFVec n e) -type Opcode = Bit +{-# ANN actual_alu InitState #-} +initstate = High -alu :: Op n e -> Op n e -> Opcode -> TFVec n e -> TFVec n e -> TFVec n e +alu :: Op n e -> Op n e -> Opcode -> Vector n e -> Vector n e -> Vector n e alu op1 op2 opc a b = case opc of Low -> op1 a b High -> op2 a b -zero_inv_alu :: Opcode -> TFVec D4 Bit -> TFVec D4 Bit -> TFVec D4 Bit -zero_inv_alu = alu (constant Low) invop +{-# ANN actual_alu TopEntity #-} +actual_alu :: (Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8)) -> Vector D4 (SizedInt D8) +--actual_alu = alu (constant Low) andop +actual_alu (opc, a, b) = alu (anyset (+) (0 :: SizedInt D8)) (andop (-)) opc a b + +runalu = P.map actual_alu sim_input