X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=HighOrdAlu.hs;h=6b11350ca951e059be3593298ae82d2b83853585;hb=4492bef13c85e9566eaeae496203f12f867e8326;hp=1ead210f0bb82dd85ceae098bdd3fb89380b5cf8;hpb=4c63601269c7097e2177c547dc36d4edecc1c648;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs
index 1ead210..6b11350 100644
--- a/HighOrdAlu.hs
+++ b/HighOrdAlu.hs
@@ -1,34 +1,39 @@
-{-# LANGUAGE TemplateHaskell #-}
+{-# LANGUAGE TemplateHaskell, ScopedTypeVariables #-}
 
 module HighOrdAlu where
 
+import qualified Prelude as P
 import Prelude hiding (
   null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr,
   zipWith, zip, unzip, concat, reverse, iterate )
 import Bits
-import Types
+-- import Types
+import Types.Data.Num.Ops
+import Types.Data.Num.Decimal.Digits
+import Types.Data.Num.Decimal.Ops
+import Types.Data.Num.Decimal.Literals
 import Data.Param.TFVec
 import Data.RangedWord
+import Data.SizedInt
 import CLasH.Translator.Annotations
 
-constant :: e -> Op D4 e
-constant e a b =
-  (e +> (e +> (e +> (singleton e))))
+constant :: NaturalT n => e -> Op n e
+constant e a b = copy e
 
 invop :: Op n Bit
 invop a b = map hwnot a
 
-andop :: Op n Bit
-andop a b = zipWith hwand a b
+andop :: (e -> e -> e) -> Op n e
+andop f a b = zipWith f a b
 
 -- Is any bit set?
 --anyset :: (PositiveT n) => Op n Bit
-anyset :: (Bit -> Bit -> Bit) -> Op D4 Bit
+anyset :: NaturalT n => (e -> e -> e) -> e -> Op n e
 --anyset a b = copy undefined (a' `hwor` b')
-anyset f a b = constant (a' `hwor` b') a b
+anyset f s a b = constant (f a' b') a b
   where 
-    a' = foldl f Low a
-    b' = foldl f Low b
+    a' = foldl f s a
+    b' = foldl f s b
 
 xhwor = hwor
 
@@ -36,9 +41,10 @@ type Op n e = (TFVec n e -> TFVec n e -> TFVec n e)
 type Opcode = Bit
 
 {-# ANN sim_input TestInput#-}
-sim_input = [ (High,$(vectorTH [High,Low,Low,Low]),$(vectorTH [High,Low,Low,Low]))
-            , (High,$(vectorTH [High,High,High,High]),$(vectorTH [High,High,High,High]))
-            , (Low,$(vectorTH [High,Low,Low,High]),$(vectorTH [High,Low,High,Low]))]
+sim_input :: [(Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8))]
+sim_input = [ (High,  $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
+            , (High,  $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
+            , (Low,   $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) ]
 
 {-# ANN actual_alu InitState #-}
 initstate = High
@@ -50,6 +56,8 @@ alu op1 op2 opc a b =
     High -> op2 a b
 
 {-# ANN actual_alu TopEntity #-}
-actual_alu :: (Opcode, TFVec D4 Bit, TFVec D4 Bit) -> TFVec D4 Bit
+actual_alu :: (Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8)) -> TFVec D4 (SizedInt D8)
 --actual_alu = alu (constant Low) andop
-actual_alu (opc, a, b) = alu (anyset xhwor) (andop) opc a b
+actual_alu (opc, a, b) = alu (anyset (+) (0 :: SizedInt D8)) (andop (-)) opc a b
+
+runalu = P.map actual_alu sim_input
\ No newline at end of file