X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Generate.hs;h=692d912e7d48c4aa8db982f211c6155131991236;hb=65c54e15c4ef306305eca6f41b19731a6a1f6b9e;hp=264f4e350099eef9dae70ccffe02f2360eef555f;hpb=7c32f78c85d0f73be7d5d436ae4ff1075c282f03;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index 264f4e3..692d912 100644 --- a/Generate.hs +++ b/Generate.hs @@ -48,10 +48,10 @@ genMapCall entity [arg, res] = genSm genScheme = AST.ForGn nPar range -- Get the entity name and port names entity_id = ent_id entity - argport = map (Monad.liftM fst) (ent_args entity) + argports = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport = mkAssocElemIndexed (head argport) (varToString arg) nPar + inport = mkAssocElemIndexed (argports!!0) (varToString arg) nPar outport = mkAssocElemIndexed resport (varToString res) nPar clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" portassigns = Maybe.catMaybes [inport,outport,clk_port] @@ -60,6 +60,34 @@ genMapCall entity [arg, res] = genSm compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions genSm = AST.GenerateSm label genScheme [] [compins] + +genZipWithCall :: + Entity + -> [CoreSyn.CoreBndr] + -> AST.GenerateSm +genZipWithCall entity [arg1, arg2, res] = genSm + where + -- Setup the generate scheme + len = (tfvec_len . Var.varType) res + label = mkVHDLExtId ("zipWithVector" ++ (varToString res)) + nPar = AST.unsafeVHDLBasicId "n" + range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + genScheme = AST.ForGn nPar range + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar + inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar + outport = mkAssocElemIndexed resport (varToString res) nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + genSm = AST.GenerateSm label genScheme [] [compins] genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements -> AST.TypeMark -- ^ type of the vector