X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Generate.hs;h=654dc8625cbc864ce49c15a9c7963d05419bda80;hb=597f1b6823417f2c4cc54549f2a9d1b9f131893c;hp=22795440fe81daf4ecfc7ba26546ae20ca695a88;hpb=500eeddbc234537b7453f7368387977ad83f0262;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index 2279544..654dc86 100644 --- a/Generate.hs +++ b/Generate.hs @@ -41,8 +41,8 @@ genMapCall :: genMapCall entity [arg, res] = genSm where -- Setup the generate scheme - len = getVectorLen res - label = mkVHDLExtId ("mapVector" ++ (bndrToString res)) + len = (tfvec_len . Var.varType) res + label = mkVHDLExtId ("mapVector" ++ (varToString res)) nPar = AST.unsafeVHDLBasicId "n" range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) genScheme = AST.ForGn nPar range @@ -51,13 +51,13 @@ genMapCall entity [arg, res] = genSm argport = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport = mkAssocElemIndexed (head argport) (bndrToString arg) nPar - outport = mkAssocElemIndexed resport (bndrToString res) nPar + inport = mkAssocElemIndexed (head argport) (varToString arg) nPar + outport = mkAssocElemIndexed resport (varToString res) nPar clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" portassigns = Maybe.catMaybes [inport,outport,clk_port] -- Generate the portmap mapLabel = "map" ++ (AST.fromVHDLId entity_id) - compins = genComponentInst mapLabel entity_id portassigns + compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions genSm = AST.GenerateSm label genScheme [] [compins] @@ -248,4 +248,4 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others) (AST.PrimName $ AST.NSimple aPar)]) -- return res - copyExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) \ No newline at end of file + copyExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)