X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Generate.hs;h=1a01a67d75d8539e4753c7d588769215c3871011;hb=9d68520884d4b1803e566ff0bb50eab9b966b909;hp=5be869459ff445576861811d7cec822ba24d70d6;hpb=969b7ddd86b69d2fc61b101961affcca0364749c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index 5be8694..1a01a67 100644 --- a/Generate.hs +++ b/Generate.hs @@ -84,73 +84,132 @@ genFCall' (Right name) _ _ = error $ "Cannot generate builtin function call assi -- | Generate a generate statement for the builtin function "map" genMap :: BuiltinBuilder -genMap = genVarArgs genMap' -genMap' (Left res) f [mapped_f, arg] = do - signatures <- getA vsSignatures - let entity = Maybe.fromMaybe - (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!") - (Map.lookup mapped_f signatures) +genMap (Left res) f [Left mapped_f, Left (Var arg)] = + -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL + -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since + -- we must index it (which we couldn't if it was a VHDL Expr, since only + -- VHDLNames can be indexed). let -- Setup the generate scheme len = (tfvec_len . Var.varType) res -- TODO: Use something better than varToString label = mkVHDLExtId ("mapVector" ++ (varToString res)) - nPar = AST.unsafeVHDLBasicId "n" + n_id = mkVHDLBasicId "n" + n_expr = idToVHDLExpr n_id range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) - genScheme = AST.ForGn nPar range - -- Get the entity name and port names - entity_id = ent_id entity - argports = map (Monad.liftM fst) (ent_args entity) - resport = (Monad.liftM fst) (ent_res entity) - -- Assign the ports - inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar - outport = mkAssocElemIndexed resport (varToVHDLId res) nPar - portassigns = Maybe.catMaybes [inport,outport] - -- Generate the portmap - mapLabel = "map" ++ (AST.fromVHDLId entity_id) - compins = mkComponentInst mapLabel entity_id portassigns - -- Return the generate functions - genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] - in - return $ [genSm] + genScheme = AST.ForGn n_id range + + -- Create the content of the generate statement: Applying the mapped_f to + -- each of the elements in arg, storing to each element in res + resname = mkIndexedName (varToVHDLName res) n_expr + argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr + in do + let (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f + let valargs = get_val_args (Var.varType real_f) already_mapped_args + app_concsms <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr]) + -- Return the generate statement + return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms] + genMap' (Right name) _ _ = error $ "Cannot generate map function call assigned to a VHDLName: " ++ show name genZipWith :: BuiltinBuilder genZipWith = genVarArgs genZipWith' genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm] -genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do - signatures <- getA vsSignatures - let entity = Maybe.fromMaybe - (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!") - (Map.lookup zipped_f signatures) +genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = let -- Setup the generate scheme len = (tfvec_len . Var.varType) res -- TODO: Use something better than varToString label = mkVHDLExtId ("zipWithVector" ++ (varToString res)) - nPar = AST.unsafeVHDLBasicId "n" + n_id = mkVHDLBasicId "n" + n_expr = idToVHDLExpr n_id range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) - genScheme = AST.ForGn nPar range - -- Get the entity name and port names - entity_id = ent_id entity - argports = map (Monad.liftM fst) (ent_args entity) - resport = (Monad.liftM fst) (ent_res entity) - -- Assign the ports - inport1 = mkAssocElemIndexed (argports!!0) (varToVHDLId arg1) nPar - inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId arg2) nPar - outport = mkAssocElemIndexed resport (varToVHDLId res) nPar - portassigns = Maybe.catMaybes [inport1,inport2,outport] - -- Generate the portmap - mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id) - compins = mkComponentInst mapLabel entity_id portassigns + genScheme = AST.ForGn n_id range + + -- Create the content of the generate statement: Applying the zipped_f to + -- each of the elements in arg1 and arg2, storing to each element in res + resname = mkIndexedName (varToVHDLName res) n_expr + argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr + argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr + in do + app_concsms <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2] -- Return the generate functions - genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] - in - return $ [genSm] -{- + return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms] + genFoldl :: BuiltinBuilder genFoldl = genVarArgs genFoldl' -genFoldl' resVal f [folded_f, startVal, inVec] = do +genFoldl' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm] +-- Special case for an empty input vector, just assign start to res +genFoldl' (Left res) _ [_, start, vec] | len == 0 = return [mkUncondAssign (Left res) (varToVHDLExpr start)] + where len = (tfvec_len . Var.varType) vec +genFoldl' (Left res) f [folded_f, start, vec] = do + -- evec is (TFVec n), so it still needs an element type + let (nvec, _) = splitAppTy (Var.varType vec) + -- Put the type of the start value in nvec, this will be the type of our + -- temporary vector + let tmp_ty = Type.mkAppTy nvec (Var.varType start) + tmp_vhdl_ty <- vhdl_ty tmp_ty + -- Setup the generate scheme + let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec)) + let block_label = mkVHDLExtId ("foldlVector" ++ (varToString start)) + let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr + let gen_scheme = AST.ForGn n_id gen_range + -- Make the intermediate vector + let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing + -- Create the generate statement + cells <- sequence [genFirstCell, genOtherCell] + let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells) + -- Assign tmp[len-1] to res + let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) + let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign] + return [AST.CSBSm block] + where + -- The vector length + len = (tfvec_len . Var.varType) vec + -- An id for the counter + n_id = mkVHDLBasicId "n" + n_expr = idToVHDLExpr n_id + -- An expression for n-1 + n_min_expr = n_expr AST.:-: (AST.PrimLit "1") + -- An expression for len-1 + len_min_expr = (AST.PrimLit $ show (len-1)) + -- An id for the tmp result vector + tmp_id = mkVHDLBasicId "tmp" + tmp_name = AST.NSimple tmp_id + -- Generate parts of the fold + genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm + genFirstCell = do + let cond_label = mkVHDLExtId "firstcell" + -- if n == 0 + let cond_scheme = AST.IfGn $ n_expr AST.:=: (AST.PrimLit "0") + -- Output to tmp[n] + let resname = mkIndexedName tmp_name n_expr + -- Input from start + let argexpr1 = varToVHDLExpr start + -- Input from vec[n] + let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_expr + app_concsms <- genApplication (Right resname) folded_f [Right argexpr1, Right argexpr2] + -- Return the conditional generate part + return $ AST.GenerateSm cond_label cond_scheme [] app_concsms + + genOtherCell = do + let cond_label = mkVHDLExtId "othercell" + -- if n > 0 + let cond_scheme = AST.IfGn $ n_expr AST.:>: (AST.PrimLit "0") + -- Output to tmp[n] + let resname = mkIndexedName tmp_name n_expr + -- Input from tmp[n-1] + let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_min_expr + -- Input from vec[n] + let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_expr + app_concsms <- genApplication (Right resname) folded_f [Right argexpr1, Right argexpr2] + -- Return the conditional generate part + return $ AST.GenerateSm cond_label cond_scheme [] app_concsms + +{- +genFoldr :: BuiltinBuilder +genFoldr = genVarArgs genFoldr' +genFoldr' resVal f [folded_f, startVal, inVec] = do signatures <- getA vsSignatures let entity = Maybe.fromMaybe (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!") @@ -159,32 +218,37 @@ genFoldl' resVal f [folded_f, startVal, inVec] = do let vecty = Type.mkAppTy vec (Var.varType startVal) vecType <- vhdl_ty vecty -- Setup the generate scheme - let len = (tfvec_len . Var.varType) inVec - let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec)) - let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal)) - let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) - let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range + let len = (tfvec_len . Var.varType) inVec + let genlabel = mkVHDLExtId ("foldrVector" ++ (varToString inVec)) + let blockLabel = mkVHDLExtId ("foldrVector" ++ (varToString startVal)) + let range = AST.DownRange (AST.PrimLit $ show (len-1)) (AST.PrimLit "0") + let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range -- Make the intermediate vector - let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing + let tmpId = mkVHDLExtId "tmp" + let tmpVec = AST.BDISD $ AST.SigDec tmpId vecType Nothing -- Get the entity name and port names let entity_id = ent_id entity let argports = map (Monad.liftM fst) (ent_args entity) let resport = (Monad.liftM fst) (ent_res entity) + -- Generate the output assignment + let assign = [mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName + (AST.NSimple tmpId) [AST.PrimLit "0"])))] -- Return the generate functions - let genSm = AST.GenerateSm genlabel genScheme [] - [ AST.CSGSm (genFirstCell (entity_id, argports, resport) - [startVal, inVec, resVal]) - , AST.CSGSm (genOtherCell (entity_id, argports, resport) + let genSm = AST.CSGSm $ AST.GenerateSm genlabel genScheme [] + [ AST.CSGSm (genFirstCell len (entity_id, argports, resport) [startVal, inVec, resVal]) - , AST.CSGSm (genLastCell (entity_id, argports, resport) + , AST.CSGSm (genOtherCell len (entity_id, argports, resport) [startVal, inVec, resVal]) ] - return $ [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]] + return $ if len > 0 then + [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] (genSm : assign)] + else + [mkUncondAssign (Left resVal) (AST.PrimName $ AST.NSimple (varToVHDLId startVal))] where - genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn + genFirstCell len (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn where - cellLabel = mkVHDLExtId "firstcell" - cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0")) + cellLabel = mkVHDLExtId "firstcell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1))) tmpId = mkVHDLExtId "tmp" nPar = AST.unsafeVHDLBasicId "n" -- Assign the ports @@ -197,16 +261,16 @@ genFoldl' resVal f [folded_f, startVal, inVec] = do compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] - genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn + genOtherCell len (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn where len = (tfvec_len . Var.varType) inVec - cellLabel = mkVHDLExtId "othercell" - cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0")) - ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1))) + cellLabel = mkVHDLExtId "othercell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:/=: (AST.PrimLit $ show (len-1))) + -- ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1))) tmpId = mkVHDLExtId "tmp" nPar = AST.unsafeVHDLBasicId "n" -- Assign the ports - inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1") + inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n+1") inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar outport = mkAssocElemIndexed resport tmpId nPar portassigns = Maybe.catMaybes [inport1,inport2,outport] @@ -215,27 +279,10 @@ genFoldl' resVal f [folded_f, startVal, inVec] = do compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] - genLastCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn - where - len = (tfvec_len . Var.varType) inVec - cellLabel = mkVHDLExtId "lastCell" - cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1))) - tmpId = mkVHDLExtId "tmp" - nPar = AST.unsafeVHDLBasicId "n" - -- Assign the ports - inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1") - inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar - outport = mkAssocElemIndexed resport tmpId nPar - portassigns = Maybe.catMaybes [inport1,inport2,outport] - -- Generate the portmap - mapLabel = "cell" ++ (AST.fromVHDLId entity_id) - compins = mkComponentInst mapLabel entity_id portassigns - -- Generate the output assignment - assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName - (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)]))) - -- Return the generate functions - cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign] + -} + + ----------------------------------------------------------------------------- -- Function to generate VHDL for applications ----------------------------------------------------------------------------- @@ -520,7 +567,8 @@ globalNameTable = Map.fromList , (plusgtId , (2, genFCall ) ) , (mapId , (2, genMap ) ) , (zipWithId , (3, genZipWith ) ) - --, (foldlId , (3, genFoldl ) ) + , (foldlId , (3, genFoldl ) ) + --, (foldrId , (3, genFoldr ) ) , (emptyId , (0, genFCall ) ) , (singletonId , (1, genFCall ) ) , (copyId , (2, genFCall ) )