X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Generate.hs;h=17c3d494e6f74aae3dbc8b491fa98a37287eec65;hb=a44db062ae75b4fe3ce28368e07323130a14fe58;hp=cc3cb675b3a405fd7a10cb1d1d973c86195f3742;hpb=8c52b6cf13be6b0080ce3353bebfd04b18336036;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index cc3cb67..17c3d49 100644 --- a/Generate.hs +++ b/Generate.hs @@ -42,7 +42,7 @@ genExprFCall fname res args = do genMapCall :: Entity -- | The entity to map -> [CoreSyn.CoreBndr] -- | The vectors - -> VHDLSession AST.GenerateSm -- | The resulting generate statement + -> VHDLSession AST.ConcSm -- | The resulting generate statement genMapCall entity [arg, res] = return $ genSm where -- Setup the generate scheme @@ -56,20 +56,19 @@ genMapCall entity [arg, res] = return $ genSm argports = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport = mkAssocElemIndexed (argports!!0) (varToString arg) nPar - outport = mkAssocElemIndexed resport (varToString res) nPar - clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" - portassigns = Maybe.catMaybes [inport,outport,clk_port] + inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar + outport = mkAssocElemIndexed resport (varToVHDLId res) nPar + portassigns = Maybe.catMaybes [inport,outport] -- Generate the portmap mapLabel = "map" ++ (AST.fromVHDLId entity_id) compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions - genSm = AST.GenerateSm label genScheme [] [compins] + genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] genZipWithCall :: Entity -> [CoreSyn.CoreBndr] - -> VHDLSession AST.GenerateSm + -> VHDLSession AST.ConcSm genZipWithCall entity [arg1, arg2, res] = return $ genSm where -- Setup the generate scheme @@ -83,16 +82,102 @@ genZipWithCall entity [arg1, arg2, res] = return $ genSm argports = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar - inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar - outport = mkAssocElemIndexed resport (varToString res) nPar - clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" - portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + inport1 = mkAssocElemIndexed (argports!!0) (varToVHDLId arg1) nPar + inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId arg2) nPar + outport = mkAssocElemIndexed resport (varToVHDLId res) nPar + portassigns = Maybe.catMaybes [inport1,inport2,outport] -- Generate the portmap mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id) compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions - genSm = AST.GenerateSm label genScheme [] [compins] + genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] + +genFoldlCall :: + Entity + -> [CoreSyn.CoreBndr] + -> VHDLSession AST.ConcSm +genFoldlCall entity [startVal, inVec, resVal] = do + let (vec, _) = splitAppTy (Var.varType inVec) + let vecty = Type.mkAppTy vec (Var.varType startVal) + vecType <- vhdl_ty vecty + -- Setup the generate scheme + let len = (tfvec_len . Var.varType) inVec + let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec)) + let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal)) + let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range + -- Make the intermediate vector + let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing + -- Get the entity name and port names + let entity_id = ent_id entity + let argports = map (Monad.liftM fst) (ent_args entity) + let resport = (Monad.liftM fst) (ent_res entity) + -- Return the generate functions + let genSm = AST.GenerateSm genlabel genScheme [] + [ AST.CSGSm (genFirstCell (entity_id, argports, resport) + [startVal, inVec, resVal]) + , AST.CSGSm (genOtherCell (entity_id, argports, resport) + [startVal, inVec, resVal]) + , AST.CSGSm (genLastCell (entity_id, argports, resport) + [startVal, inVec, resVal]) + ] + return $ AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm] + where + genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn + where + cellLabel = mkVHDLExtId "firstcell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0")) + tmpId = mkVHDLExtId "tmp" + nPar = AST.unsafeVHDLBasicId "n" + -- Assign the ports + inport1 = mkAssocElem (argports!!0) (varToString startVal) + inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar + outport = mkAssocElemIndexed resport tmpId nPar + portassigns = Maybe.catMaybes [inport1,inport2,outport] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] + genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn + where + len = (tfvec_len . Var.varType) inVec + cellLabel = mkVHDLExtId "othercell" + cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0")) + ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1))) + tmpId = mkVHDLExtId "tmp" + nPar = AST.unsafeVHDLBasicId "n" + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1") + inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar + outport = mkAssocElemIndexed resport tmpId nPar + portassigns = Maybe.catMaybes [inport1,inport2,outport] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] + genLastCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn + where + len = (tfvec_len . Var.varType) inVec + cellLabel = mkVHDLExtId "lastCell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1))) + tmpId = mkVHDLExtId "tmp" + nPar = AST.unsafeVHDLBasicId "n" + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1") + inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar + outport = mkAssocElemIndexed resport tmpId nPar + portassigns = Maybe.catMaybes [inport1,inport2,outport] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Generate the output assignment + assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName + (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)]))) + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign] + -- Returns the VHDLId of the vector function with the given name for the given -- element type. Generates -- this function if needed. @@ -158,7 +243,7 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "1")) ])) Nothing -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1) @@ -167,7 +252,7 @@ genUnconsVectorFuns elemTM vectorTM = AST.PrimName (AST.NSimple aPar) AST.:&: vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1") ((AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing)) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)) AST.:-: AST.PrimLit "1")) replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) vecSlice init last = AST.PrimName (AST.NSlice @@ -183,7 +268,7 @@ genUnconsVectorFuns elemTM vectorTM = lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1"]))) initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM -- variable res : fsvec_x (0 to vec'length-2); @@ -193,14 +278,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "2")) ])) Nothing -- resAST.:= vec(0 to vec'length-2) initExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "2")) initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM @@ -211,14 +296,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "2")) ])) Nothing -- res AST.:= vec(1 to vec'length-1) tailExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimLit "1") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1")) tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM, @@ -246,14 +331,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ])) Nothing -- res AST.:= vec(n to vec'length-1) dropExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimName $ AST.NSimple nPar) (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1")) dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM, @@ -265,7 +350,7 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing))])) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))])) Nothing plusgtExpr = AST.NSimple resId AST.:= ((AST.PrimName $ AST.NSimple aPar) AST.:&: